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* i965/fs: Enumerate logical fb writes argumentsBen Widawsky2015-10-213-21/+29
| | | | | | | | | | | | | | | | | | | Gen9 adds the ability to write out a stencil value, so we need to expand the virtual payload by one. Abstracting this now makes that change easier to read. I was admittedly confused early on about some of the hardcoding. If people believe the resulting code is inferior, I am not super attached to the patch. v2: Remove explicit numbering from the enumeration (Matt). Use a real naming scheme, and reference it in the opcode definition (Curro) Add a missed hardcoded logical position in get_lowered_simd_width (Ben) Add an assertion to make sure the component numbering is correct (Ben) Cc: Matt Turner <[email protected]> Cc: Francisco Jerez <[email protected]> Signed-off-by: Ben Widawsky <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* svga: fix clip plane regression after recent tgsi_scan changeBrian Paul2015-10-211-2/+2
| | | | | | | | | Before the change "tgsi/scan: use properties for clip/cull distance writemasks", the tgsi_shader_info::num_written_clipdistance field was a multiple of four, now it's an accurate count. In the svga driver, we need a minor change to the loop test. Reviewed-by: Charmaine Lee <[email protected]>
* i965: Implement gl_InvocationID.Kenneth Graunke2015-10-211-0/+13
| | | | | | | It's stored in bits 31:27 of g1 (along with the URB handles). Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Kristian Høgsberg <[email protected]>
* i965: Implement nir_intrinsic_load_primitive.Kenneth Graunke2015-10-211-0/+8
| | | | | Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Kristian Høgsberg <[email protected]>
* i965: Add a fs_visitor constructor that takes a brw_gs_compile.Kenneth Graunke2015-10-212-3/+39
| | | | | | | | | | | Unlike the vs/wm structs, brw_gs_compile is actually useful: it contains the input VUE map and information about the control data headers. Passing this in allows us to share that code in brw_gs.c, and calculate them before deciding on vec4 vs. scalar mode, as it's independent of that choice. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Kristian Høgsberg <[email protected]>
* i965: Add a brw->scalar_gs flag controlled by INTEL_SCALAR_GS=1.Kenneth Graunke2015-10-213-1/+8
| | | | | | | | | | | This patch introduces a brw->scalar_gs flag, similar to brw->scalar_vs, which controls whether or not to use SIMD8 geometry shaders. For now, we control it via a new environment variable, INTEL_SCALAR_GS. This provides a convenient way to try it out. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Kristian Høgsberg <[email protected]>
* i965: Make emit_urb_writes() reserve space for GS header information.Kenneth Graunke2015-10-211-2/+16
| | | | | | | | | | | Geometry shaders have additional header data at the beginning of their output URB entries. Shaders that use EndPrimitive() or multiple streams have a control data header; shaders with a dynamic vertex count have an additional vec4 slot to hold the 32-bit vertex count (and 96 bits of padding). Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Kristian Høgsberg <[email protected]>
* i965: Make emit_urb_writes() only set EOT for the VS.Kenneth Graunke2015-10-211-1/+1
| | | | | | | | | The GS will emit a bunch of vertices, and we don't want to do an EOT prematurely. We'll emit GS_OPCODE_THREAD_END when we want to terminate the thread. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Kristian Høgsberg <[email protected]>
* i965: Make fs_visitor::emit_urb_writes reusable for scalar GS.Kenneth Graunke2015-10-211-7/+7
| | | | | | | | GS doesn't have ClampVertexColor, and we don't want to go through VS structures. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Kristian Høgsberg <[email protected]>
* i965: Introduce a brw_vue_prog_data::include_vue_handles flag.Kenneth Graunke2015-10-212-0/+5
| | | | | | | | | Tessellation shaders and SIMD8 geometry shaders may need to resort to the pull model for inputs at times. When set, the state upload code will tell the hardware to provide URB handles for input data. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Kristian Høgsberg <[email protected]>
* i965: Introduce a new SHADER_OPCODE_URB_READ_SIMD8 opcode.Kenneth Graunke2015-10-215-0/+40
| | | | | | | | | | | | In scalar mode, geometry shader inputs can easily take up hundreds of registers. This makes pushing VUE entries impractical; we'll need to resort to the pull model in some cases. To support this, we introduce a new opcode corresponding to the "URB Read SIMD8" message. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Kristian Høgsberg <[email protected]>
* i965: Introduce new SHADER_OPCODE_URB_WRITE_SIMD8_MASKED/PER_SLOT opcodes.Kenneth Graunke2015-10-215-0/+33
| | | | | | | | | | | | | In the vec4 backend, we have a vec4_instruction::urb_write_flags field. There are many kinds of flags for SIMD4x2 messages. However, there are really only two (per-slot offset, use channel masks) for SIMD8 messages. Rather than adding a boolean flag for per-slot offsets (polluting all instructions), I decided to just make three new opcodes. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Kristian Høgsberg <[email protected]>
* i965/gs: Do prog_data setup and other calculations in brw_compile_gsJason Ekstrand2015-10-214-220/+222
| | | | | | | | | | | | | | | | This commit moves the large pile of setup calculations we have to do for geometry shaders out of brw_gs_emit and into brw_compile_gs. This has a couple of nice implications. First, it's less work that the caller of brw_compile_gs has to do. Second, it's consistent with the vertex and fragment stages. Finally, it allows us to put brw_gs_compile back behind the API boundary where it belongs. v2 (Jason Ekstrand): - Pull the changes to use nir info into a separate patch - Put brw_gs_compile into brw_shader.h rather than brw_vec4_gs_visitor.h so that we can use it for scalar GS. Reviewed-by: Kenneth Graunke <[email protected]>
* i965/gs: Use NIR info for setting up prog_dataJason Ekstrand2015-10-211-11/+13
| | | | | | | | | | Previously, we were pulling bits from GL data structures in order to set up the prog_data. However, in this brave new world of NIR, we want to be pulling it out of the NIR shader whenever possible. This way, we can move all this setup code into brw_compile_gs without depending on the old GL stuff. Reviewed-by: Kenneth Graunke <[email protected]>
* i965/gs: Pull prog_data out of brw_gs_compileJason Ekstrand2015-10-217-79/+80
| | | | Reviewed-by: Kenneth Graunke <[email protected]>
* i965/gs: Use NIR instead of the brw_geometry_program for GS metadataJason Ekstrand2015-10-214-12/+9
| | | | | | With this, we can remove the geometry program from brw_gs_compile. Reviewed-by: Kenneth Graunke <[email protected]>
* i965/gs: Move the mem_ctx argument to brw_compile_gsJason Ekstrand2015-10-213-4/+4
| | | | | | This makes it better match the other brw_compile_* functions. Reviewed-by: Kenneth Graunke <[email protected]>
* i965/gs: Set static_vertex_count unconditionally on GEN8+Jason Ekstrand2015-10-211-1/+1
| | | | | | We always have NIR, so there's no reason for the check. Reviewed-by: Kenneth Graunke <[email protected]>
* nir: Constify nir_gs_count_verticesJason Ekstrand2015-10-212-2/+2
| | | | Reviewed-by: Kenneth Graunke <[email protected]>
* nir/info: Add more information about geometry shadersJason Ekstrand2015-10-212-0/+16
| | | | Reviewed-by: Kenneth Graunke <[email protected]>
* i965: (trivial) rename computes stencil to gen9Ben Widawsky2015-10-211-1/+1
| | | | | | | | | | | | | | | All the documentation I can find says that this bit (and functionality) only exists on SKL+. Since the bit isn't yet used, there is no real impact here. The original code was added by Ken here (a surprisingly long time ago): commit f3c6d6f1e151f6a44a76038dccebe4434038dcb1 Author: Kenneth Graunke <[email protected]> Date: Thu Nov 29 21:00:27 2012 -0800 i965: Update 3DSTATE_PS, 3DSTATE_WM, and add 3DSTATE_PS_EXTRA. Signed-off-by: Ben Widawsky <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965: Correct the comment about fb write payloadBen Widawsky2015-10-211-2/+2
| | | | | Signed-off-by: Ben Widawsky <[email protected]> Reviewed-by: Francisco Jerez <[email protected]>
* mesa/glformats: Undo code changes from _mesa_base_tex_format() moveNanley Chery2015-10-211-141/+8
| | | | | | | | | | | | | | The refactoring commit, c6bf1cd, accidentally reverted cd49b97 and 99b1f47. These changes caused more code to be added to the function and removed the existing support for ASTC. This patch reverts those modifications. v2. Actually include ASTC support again. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=92221 Cc: "11.0" <[email protected]> Signed-off-by: Nanley Chery <[email protected]> Reviewed-by: Emil Velikov <[email protected]>
* i965: Mark compacted 3-src instructions as Gen8+.Matt Turner2015-10-211-16/+16
| | | | Reviewed-by: Iago Toral Quiroga <[email protected]>
* i965: Add const to brw_compact_inst_bits.Matt Turner2015-10-211-2/+2
| | | | Reviewed-by: Iago Toral Quiroga <[email protected]>
* i965: Add mask_control_ex field and handle it in compaction.Matt Turner2015-10-212-0/+6
| | | | | | | | Documentation is sparse, but it appears to have existed on G45 and ILK as a second bit extension of the mask_control field. Setting the pair of bits to 0b11 enables "NoCMask". Reviewed-by: Iago Toral Quiroga <[email protected]>
* i965: Add devinfo->gen assertions for acc_wr_control.Matt Turner2015-10-211-3/+3
| | | | | | ... and for flag_subreg_nr since it's right near by. Reviewed-by: Iago Toral Quiroga <[email protected]>
* i965: Prepare for next commit by adding more whitespace.Matt Turner2015-10-211-14/+14
| | | | | | | We're going to add a field with a longer name that wouldn't align with the rest. Reviewed-by: Iago Toral Quiroga <[email protected]>
* i965: Compact acc_wr_control only on Gen6+.Matt Turner2015-10-211-2/+8
| | | | | | | | It only exists on Gen6+, and the next patches will add compaction support for the (unused) field in the same location on earlier platforms. Reviewed-by: Iago Toral Quiroga <[email protected]>
* i965: Add devinfo parameter to brw_compact_inst_* funcs.Matt Turner2015-10-212-57/+91
| | | | | | | | | The next commit will add assertions dependent on devinfo->gen. Use compact()/uncompact() macros where possible, like the 3-src code does. Reviewed-by: Iago Toral Quiroga <[email protected]>
* i965/vec4: Don't emit MOVs for unused URB slots.Matt Turner2015-10-212-6/+14
| | | | | | | | | | Otherwise we'd emit a MOV from the null register (which isn't allowed). Helps 24 programs in shader-db (the geometry shaders in GSCloth): instructions in affected programs: 302 -> 262 (-13.25%) Reviewed-by: Iago Toral Quiroga <[email protected]>
* osmesa: Expose GL entry points for Windows build via DEF file.Nigel Stewart2015-10-212-0/+674
| | | | | | Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=92437 CC: "10.6 11.0" <[email protected]> Signed-off-by: Jose Fonseca <[email protected]>
* configure.ac: ensure RM is setJonathan Gray2015-10-211-0/+2
| | | | | | | | | | | GNU make predefines RM to rm -f but this is not required by POSIX so ensure that RM is set. This fixes "make clean" on OpenBSD. v2: use AC_CHECK_PROG Signed-off-by: Jonathan Gray <[email protected]> CC: "10.6 11.0" <[email protected]> Reviewed-by: Emil Velikov <[email protected]>
* i965/fs: Disable opt_sampler_eot for more message typesNeil Roberts2015-10-211-6/+8
| | | | | | | | | | | In bfdae9149e0 I disabled the opt_sampler_eot optimisation for TG4 message types because I found by experimentation that it doesn't work. I wrote in the comment that I couldn't find any documentation for this problem. However I've now found the documentation and it has additional restrictions on further message types so this patch updates the comment and adds the others. Reviewed-by: Matt Turner <[email protected]>
* i965: Remove block arg from foreach_inst_in_block_*_starting_fromNeil Roberts2015-10-215-9/+8
| | | | | | | | | Since 49374fab5d793 these macros no longer actually use the block argument. I think this is worth doing to make the macros easier to use because they already have really long names and a confusing set of arguments. Reviewed-by: Matt Turner <[email protected]>
* glsl: check for arrays of arrays when assigning explicit locationsTimothy Arceri2015-10-211-1/+2
| | | | | | | | This fixes assigning explicit locations in the CTS test: ES31-CTS.explicit_uniform_location.uniform-loc-arrays-of-arrays Reviewed-by: Tapani Pälli <[email protected]>
* glsl: add is_array_of_arrays() helperTimothy Arceri2015-10-211-0/+5
| | | | | | As suggested by Ian Romanick Reviewed-by: Tapani Pälli <[email protected]>
* glsl: Fix bad indentation in bit_logic_result_type().Kenneth Graunke2015-10-201-47/+47
| | | | | | | | The first level of indentation was using 4 spaces. Mesa uses 3. Trivial. Signed-off-by: Kenneth Graunke <[email protected]>
* glsl: add AoA support to subroutinesTimothy Arceri2015-10-212-6/+39
| | | | | | | | | | | | | | | process_parameters() will now be called earlier because we need actual_parameters processed earlier so we can use it with match_subroutine_by_name() to get the subroutine variable, we need to do this inside the recursive function generate_array_index() because we can't create the ir_dereference_array() until we have gotten to the outermost array. For the remainder of the array dimensions the type doesn't matter so we can just use the existing _mesa_ast_array_index_to_hir() function to process the ast. Reviewed-by: Dave Airlie <[email protected]>
* glsl: fix record type detection in explicit location assignTapani Pälli2015-10-211-1/+1
| | | | | | | | | | | | | Check current_var directly instead of using the passed in record_type. This fixes following failing CTS test: ES31-CTS.explicit_uniform_location.uniform-loc-types-structs No Piglit regressions. Signed-off-by: Tapani Pälli <[email protected]> Reviewed-by: Marta Lofstedt <[email protected]> Reviewed-by: Samuel Iglesias Gonsálvez <[email protected]>
* glsl: do not try to reserve explicit locations for buffer variablesTapani Pälli2015-10-211-2/+2
| | | | | | | | Explicit locations are only used with uniform variables. Signed-off-by: Tapani Pälli <[email protected]> Reviewed-by: Marta Lofstedt <[email protected]> Reviewed-by: Samuel Iglesias Gonsálvez <[email protected]>
* glsl: skip buffer variables when filling UniformRemapTableTapani Pälli2015-10-211-2/+5
| | | | | | | | | | UniformRemapTable is used only for remapping user specified uniform locations to driver internally used ones, shader storage buffer variables should not utilize uniform locations. Signed-off-by: Tapani Pälli <[email protected]> Reviewed-by: Marta Lofstedt <[email protected]> Reviewed-by: Samuel Iglesias Gonsálvez <[email protected]>
* svga: add switch case for PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINTBrian Paul2015-10-201-0/+2
| | | | | | | | A third instance of this was needed but missed in the previous commit. Return 32 as for the two other cases. Reviewed-by: Roland Scheidegger <[email protected]> Reviewed-by: Charmaine Lee <[email protected]>
* draw: fix splitting of line loops (v2)Brian Paul2015-10-204-8/+32
| | | | | | | | | | | | | | | | | When the draw module splits long line loops, the sections are emitted as line strips. But the primitive type wasn't set correctly so each section was being drawn as a loop, introducing extra line segments. To fix this, we pass a new DRAW_LINE_LOOP_AS_STRIP flag to the run() function. The linear/elt_run() functions have to check for this flag and set their primitive type accordingly. No piglit regressions. Fixes piglit's lineloop with -count 4097 or higher. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=81174 Reviewed-by: Roland Scheidegger <[email protected]>
* i965/gen9: Remove temporary variable 'bpp' in tr_mode_..._texture_alignment()Anuj Phogat2015-10-201-10/+6
| | | | | Signed-off-by: Anuj Phogat <[email protected]> Reviewed-by: Topi Pohjolainen <[email protected]>
* i965/gen9: Remove temporary variable 'align_yf' in ↵Anuj Phogat2015-10-201-17/+9
| | | | | | | tr_mode_..._texture_alignment() Signed-off-by: Anuj Phogat <[email protected]> Reviewed-by: Topi Pohjolainen <[email protected]>
* i965/gen9: Remove parameter 'brw' from tr_mode_..._texture_alignment()Anuj Phogat2015-10-201-7/+7
| | | | | | | V2: Rebased on master. Signed-off-by: Anuj Phogat <[email protected]> Reviewed-by: Topi Pohjolainen <[email protected]>
* i965/gen9: Reuse YF alignment tables in tr_mode_..._texture_alignment()Anuj Phogat2015-10-201-24/+22
| | | | | | | | Patch just does some refactoring to make the code look better. No functional changes in here. Signed-off-by: Anuj Phogat <[email protected]> Reviewed-by: Topi Pohjolainen <[email protected]>
* vbo: convert display list GL_LINE_LOOP prims to GL_LINE_STRIPBrian Paul2015-10-201-0/+53
| | | | | | | | | | | | | When a long GL_LINE_LOOP prim was split across primitives we drew stray lines. See previous commit for details. This patch converts GL_LINE_LOOP prims into GL_LINE_STRIP prims so that drivers don't have to worry about the _mesa_prim::begin/end flags. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=81174 Reviewed-by: Jose Fonseca <[email protected]> Acked-by: Sinclair Yeh <[email protected]>
* vbo: fix GL_LINE_LOOP stray line bugBrian Paul2015-10-203-3/+56
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When long GL_LINE_LOOP primitives don't fit in one vertex buffer they have to be split across buffers. The code to do this was basically correct but drivers had to pay special attention to the _mesa_prim::begin,end flags in order to draw the sections of the line loop properly. Apparently, the only drivers to do this were those using the old 'tnl' module for software vertex processing. Now we convert the split pieces of GL_LINE_LOOP prims into GL_LINE_STRIP primitives so that drivers don't have to worry about the special begin/end flags. The only time a driver will get a GL_LINE_LOOP prim is when the whole thing fits in one vertex buffer. Mostly fixes bug 81174, but not completely. There's another bug somewhere in the src/gallium/auxiliary/draw/ code. If the piglit lineloop test is run with -count 4096, rendering is correct, but with -count 4097 there are stray lines. 4096 is a magic number in the draw code (search for "4096"). Also note that this does not fix long line loops in display lists. The next patch fixes that. v2: fix incorrect -1 in vbo_compute_max_verts(), per Charmaine. Remove incorrect assertion which was added in vbo_copy_vertices(). Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=81174 Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=49779 Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=28130 Reviewed-by: Marek Olšák <[email protected]> Reviewed-by: Jose Fonseca <[email protected]> Reviewed-by: Sinclair Yeh <[email protected]>
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