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* st/omx_bellagio: add picture profile and entry pointBoyuan Zhang2018-03-021-0/+2
| | | | | | | | | Profile and entry point were missing in the picture structure. Therefore, add them back. Signed-off-by: Boyuan Zhang <[email protected]> Reviewed-by: Leo Liu <[email protected]> Reviewed-by: Christian König <[email protected]>
* radeonsi: fix radeon create encoder returnBoyuan Zhang2018-03-021-1/+1
| | | | | | | | | | | Previous patch missed a "return" when trying to modify the create encoder function, which made the whole logic fail. Therefore, add the return back. Fixes: b38b208ff8886e799d6a2 "radeonsi:create uvd hevc enc entry" Signed-off-by: Boyuan Zhang <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Reviewed-by: Eric Engestrom <[email protected]>
* loader: Add support for platform and host1x bussesThierry Reding2018-03-021-0/+27
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | ARM SoCs usually have their DRM/KMS devices on the platform bus, so add support for this bus in order to allow use of the DRI_PRIME environment variable with those devices. While at it, also support the host1x bus, which is effectively the same but uses an additional layer in the bus hierarchy. Note that it isn't enough to support the bus that has the rendering GPU because the loader code will also try to construct an ID path tag for a scanout-only device if it is the default that is being opened. The ID path tag for a device can be obtained by running udevadm info on the device node, as shown in this example on NVIDIA Tegra: $ udevadm info /dev/dri/card0 | grep ID_PATH_TAG E: ID_PATH_TAG=platform-50000000_host1x The corresponding OF_FULLNAME property, from which the ID_PATH_TAG is constructed, can be found in the sysfs "uevent" attribute for the card0 device's parent: $ grep OF_FULLNAME /sys/devices/platform/50000000.host1x/drm/uevent OF_FULLNAME=/host1x@50000000 Similarily, /dev/dri/card1 corresponds to the GPU: $ udevadm info /dev/dri/card1 | grep ID_PATH_TAG E: ID_PATH_TAG=platform-57000000_gpu and: $ grep OF_FULLNAME /sys/devices/platform/57000000.gpu/uevent OF_FULLNAME=/gpu@57000000 Changes in v2: - avoid confusing pre-increment in strdup() - add examples of tags to commit message Reviewed-by: Eric Engestrom <[email protected]> Reviewed-by: Emil Velikov <[email protected]> Signed-off-by: Thierry Reding <[email protected]>
* disk cache: Link with -latomic if necessaryThierry Reding2018-03-022-1/+18
| | | | | | | | | | | | | | | | | | | | | | | | | | The disk cache implementation uses 64-bit atomic operations. For some architectures, such as 32-bit ARM, GCC will not be able to translate these operations into atomic, lock-free instructions and will instead rely on the external atomics library to provide these operations. Check at configuration time whether or not linking against libatomic is necessary and if so, create a dependency that can be used while linking the mesautil library. This is the meson equivalent of 2ef7f23820a6 ("configure: check if -latomic is needed for __atomic_*"). For some background information on this, see: https://gcc.gnu.org/wiki/Atomic/GCCMM Changes in v2: - clarify meaning of lock-free in commit message - fix build if -latomic is not necessary Acked-by: Matt Turner <[email protected]> Reviewed-by: Dylan Baker <[email protected]> Signed-off-by: Thierry Reding <[email protected]>
* radv: do not set pending_reset_query in BeginCommandBuffer()Samuel Pitoiset2018-03-021-7/+0
| | | | | | | | | | | | | This is just useless for two reasons: 1) flush_bits is not set accordingly, so nothing will be flushed in BeginQuery(). 2) we always flush caches in EndCommandBuffer(), so if a reset is done in a previous command buffer we are safe. Cc: "18.0" <[email protected]> Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Alex Smith <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* r600/cayman: fix fragcood loading recip generation.Dave Airlie2018-03-021-1/+1
| | | | | | | | This fixes some hangs seen where the recip_ieee opcodes would end up split across the wrong slots. Cc: <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* i965: Allow 48-bit addressing on Gen8+.Kenneth Graunke2018-03-017-18/+127
| | | | | | | | | | | | | | | | | This allows most GPU objects to use the full 48-bit address space offered by Gen8+ platforms, rather than being stuck with 32-bit. This expands the available GPU memory from 4G to 256TB or so. A few objects - instruction, scratch, and vertex buffers - need to remain pinned in the low 4GB of the address space for various reasons. We default everything to 48-bit but disable it in those cases. Thanks to Jason Ekstrand for blazing this trail in anv first and finding the nasty undocumented hardware issues. This patch simply rips off all of his findings. Reviewed-by: Jordan Justen <[email protected]> Acked-by: Jason Ekstrand <[email protected]>
* i965: Shorten the name of the workaround BO.Kenneth Graunke2018-03-011-3/+1
| | | | | This makes the name shorter in debug printouts. If "workaround_bo" is good enough for the code, it's probably good enough for debugging.
* i965: Add debugging code to dump the validation list.Kenneth Graunke2018-03-011-0/+22
| | | | | When anything goes wrong with this code, dumping the validation list is a useful way to figure out what's happening.
* intel/fs: Set up sampler message headers in the visitor on gen7+Jason Ekstrand2018-03-012-22/+39
| | | | | | | | | | | | | | This gives the scheduler visibility into the headers which should improve scheduling. More importantly, however, it lets the scheduler know that the header gets written. As-is, the scheduler thinks that a texture instruction only reads it's payload and is unaware that it may write to the first register so it may reorder it with respect to a read from that register. This is causing issues in a couple of Dota 2 vertex shaders. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=104923 Cc: [email protected] Reviewed-by: Francisco Jerez <[email protected]>
* ac: fix nir_intrinsic_shared_atomic_comp_swap handlingTimothy Arceri2018-03-021-1/+1
| | | | | | | | | | Following on from 49879f377870 this makes sure we use the correct src index. Fixes cts test: KHR-GL46.compute_shader.atomic-case3 Reviewed-by: Dave Airlie <[email protected]>
* st/glsl_to_nir: simplify st_nir_assign_var_locations() and fix for fs outputsTimothy Arceri2018-03-021-17/+13
| | | | | | | | | | | | | | | We only need to check for previously processed location on user defined varyings as they are the only ones that support component packing. Therefore a single instance of processed_locs can be shared by regular varyings and patches. For simplicity we make processed_locs an array in order to handle dual source bleanding. Fixes the follow piglit test on radeonsi: tests/spec/arb_enhanced_layouts/execution/component-layout/fs-output.shader_test Reviewed-by: Dave Airlie <[email protected]>
* anv: Enable MSAA fast-clearsJason Ekstrand2018-03-011-4/+7
| | | | | | | This speeds up the Sascha Willems multisampling demo by around 25% when using 8x or 16x MSAA. Reviewed-by: Samuel Iglesias Gonsálvez <[email protected]>
* anv/cmd_buffer: Add support for MCS fast-clears and resolvesJason Ekstrand2018-03-011-5/+39
| | | | Reviewed-by: Samuel Iglesias Gonsálvez <[email protected]>
* anv/cmd_buffer: Add helpers for computing resolve predicatesJason Ekstrand2018-03-011-10/+64
| | | | | | | We'll want to re-use the complex resolve predicate computations for MCS resolves so it's nice to have them as helper functions. Reviewed-by: Samuel Iglesias Gonsálvez <[email protected]>
* anv/cmd_buffer: Handle MCS identical to CCS_E in compute_aux_usageJason Ekstrand2018-03-011-9/+5
| | | | | | | | This doesn't actually do anything because att_state->fast_clear is determined based on the return value of anv_layout_to_fast_clear_type which currently returns NONE for multisampled images. Reviewed-by: Samuel Iglesias Gonsálvez <[email protected]>
* anv/blorp: Pass the clear address to blorp for subpass MSAA resolvesJason Ekstrand2018-03-011-0/+6
| | | | Reviewed-by: Samuel Iglesias Gonsálvez <[email protected]>
* anv/blorp: Allow indirect clear colors on blorp sources on gen7Jason Ekstrand2018-03-011-2/+2
| | | | Reviewed-by: Samuel Iglesias Gonsálvez <[email protected]>
* anv/blorp: Add partial clear support to anv_image_mcs_opJason Ekstrand2018-03-011-1/+14
| | | | Reviewed-by: Samuel Iglesias Gonsálvez <[email protected]>
* intel/blorp: Add indirect clear color support to mcs_partial_resolveJason Ekstrand2018-03-013-10/+70
| | | | | | | | | | This is a bit complicated because we have to get the indirect clear color in there somehow. In order to not do any more work in the shader than needed, we set it up as it's own vertex binding which points directly at the clear color address specified by the client. Acked-by: Samuel Iglesias Gonsálvez <[email protected]> Reviewed-by: Topi Pohjolainen <[email protected]>
* intel/blorp: Add a helper for filling out VERTEX_BUFFER_STATEJason Ekstrand2018-03-011-36/+33
| | | | | | | There are enough #ifs in there that it's kind-of pointless to duplicate it for each buffer. Reviewed-by: Samuel Iglesias Gonsálvez <[email protected]>
* i965: Fix RELOC_WRITE typo in brw_store_data_imm64()Andriy Khulap2018-03-011-1/+1
| | | | | | | | | | Fixes: 6c530ad11605 ("i965: Reduce passing 2x32b of reloc_domains to 2 bits") Signed-off-by: Andriy Khulap <[email protected]> Signed-off-by: Vadym Shovkoplias <[email protected]> Reviewed-by: Chris Wilson <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* gallium/util: use sockets on PIPE_OS_UNIX in u_networkJonathan Gray2018-03-012-10/+4
| | | | | | | | Instead of listing all the UNIX PIPE_OS platforms just use PIPE_OS_UNIX. Makes BSD sockets available on PIPE_OS_BSD. Signed-off-by: Jonathan Gray <[email protected]> Reviewed-by: Brian Paul <[email protected]>
* util: use clock_gettime() on PIPE_OS_BSDJonathan Gray2018-03-011-1/+1
| | | | | | | | OpenBSD, FreeBSD, NetBSD and DragonFlyBSD all have clock_gettime() so use it when PIPE_OS_BSD is defined. Signed-off-by: Jonathan Gray <[email protected]> Reviewed-by: Brian Paul <[email protected]>
* nir/search: Include 8 and 16-bit support in construct_valueJose Maria Casanova Crespo2018-03-011-0/+15
| | | | Reviewed-by: Jason Ekstrand <[email protected]>
* nir/search: Support 8 and 16-bit constants in match_valueJason Ekstrand2018-03-011-0/+20
| | | | Reviewed-by: Jose Maria Casanova Crespo <[email protected]>
* travis: make Meson find the proper llvm-configAndres Gomez2018-03-011-4/+26
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Travis CI has moved to LLVM 5.0, and meson is detecting automatically the available version in /usr/local/bin based on the PATH env variable order preference. As for 0.44.x, Meson cannot receive the path to the llvm-config binary as a configuration parameter. See https://github.com/mesonbuild/meson/issues/2887 and https://github.com/dcbaker/meson/commit/7c8b6ee3fa42f43c9ac7dcacc61a77eca3f1bcef We want to use the custom (APT) installed version. Therefore, let's make Meson find our wanted version sooner than the one at /usr/local/bin Once this is corrected, we would still need a patch similar to: https://lists.freedesktop.org/archives/mesa-dev/2017-December/180217.html v2: Create the link only to the specificly wanted LLVM version (Gert). Cc: Eric Engestrom <[email protected]> Cc: Dylan Baker <[email protected]> Cc: Emil Velikov <[email protected]> Cc: Juan A. Suarez Romero <[email protected]> Cc: Gert Wollny <[email protected]> Cc: Jon Turney <[email protected]> Signed-off-by: Andres Gomez <[email protected]> Reviewed-and-Tested-by: Eric Engestrom <[email protected]> Reviewed-by: Dylan Baker <[email protected]> Reviewed-by: Juan A. Suarez <[email protected]> Reviewed-By: Gert Wollny <[email protected]> Reviewed-by: Emil Velikov <[email protected]>
* meson: fix LLVM version detection when <= 3.4Andres Gomez2018-03-011-1/+8
| | | | | | | | | | | | | | | | | | | | | | | 3 digits versions in LLVM only started from 3.4.1 on. Hence, even if you can perfectly build with an old LLVM (< 3.4.1) in the system while not needing LLVM at all (auto), when passing through the LLVM version detection code, meson will fail when accessing "_llvm_version[2]" due to: "Index 2 out of bounds of array of size 2." v2: Properly compare LLVM version and set patch version to 0 if < 3.4.1 (Eric). v3: Improve the commit log explanation (Eric). Cc: Dylan Baker <[email protected]> Cc: Eric Engestrom <[email protected]> Signed-off-by: Andres Gomez <[email protected]> Reviewed-by: Dylan Baker <[email protected]> Reviewed-by: Emil Velikov <[email protected]> Reviewed-by: Eric Engestrom <[email protected]>
* i965/sbe: fix number of inputs for active componentsIago Toral Quiroga2018-03-011-4/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In 16631ca30ea6 we fixed gen9 active components to account for padded inputs in the URB, which we can have with SSO programs. To do that, instead of going through the bitfield of inputs (which doesn't include padding information), we compute the number of inputs from the size of the URB entry. Unfortunately, there are some special inputs that are not stored in the URB and that we also need to account for. These special inputs are identified and handled during calculate_attr_overrides(). Instead of keeping track of the exact number of inputs, we just program active components for all possible inputs like we do in anvil. This fixes a regression in a WebGL program that uses Point Sprite functionality (specifically, VARYING_SLOT_PNTC). v2: - Add 'Fixes' tag (Mark Janes) - make no_vue_inputs int instead of uint32_t, and add const qualifier to num_inputs variable (Ian) v3: - Do not try to count inputs correctly, just program all input slots like we do in anvil (Ken) Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=105224 Fixes: 16631ca30ea6 (i965/sbe: fix active components for SSO programs with over 16 inputs) Reviewed-by: Kenneth Graunke <[email protected]>
* radv: only emit cache flushes when the pool size is large enoughSamuel Pitoiset2018-03-013-11/+15
| | | | | | | | This is an optimization which reduces the number of flushes for small pool buffers. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* radv: keep track of the query pool sizeSamuel Pitoiset2018-03-012-5/+5
| | | | | Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* radv: make sure to emit cache flushes before starting a querySamuel Pitoiset2018-03-013-7/+33
| | | | | | | | | | | If the query pool has been previously resetted using the compute shader path. Fixes: a41e2e9cf5 ("radv: allow to use a compute shader for resetting the query pool") Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=105292 Cc: "18.0" <[email protected]> Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* nir/serialize: handle var->name being NULLAlejandro Piñeiro2018-03-011-1/+2
| | | | | | | | var->name could be NULL under ARB_gl_spirv for example. And in any case, the code is already handing var name being NULL when reading a variable, so it is consistent to do it writing a variable too. Reviewed-by: Timothy Arceri <[email protected]>
* anv: Enable VK_KHR_16bit_storage for PushConstantJose Maria Casanova Crespo2018-02-281-1/+1
| | | | | | Enables storagePushConstant16 features of VK_KHR_16bit_storage for Gen8+. Reviewed-by: Jason Ekstrand <[email protected]>
* spirv/i965/anv: Relax push constant offset assertions being 32-bit alignedJose Maria Casanova Crespo2018-02-283-9/+10
| | | | | | | | | | | | | | | | The introduction of 16-bit types with VK_KHR_16bit_storages implies that push constant offsets could be multiple of 2-bytes. Some assertions are updated so offsets should be just multiple of size of the base type but in some cases we can not assume it as doubles aren't aligned to 8 bytes in some cases. For 16-bit types, the push constant offset takes into account the internal offset in the 32-bit uniform bucket adding 2-bytes when we access not 32-bit aligned elements. In all 32-bit aligned cases it just becomes 0. v2: Assert offsets to be aligned to the dest type size. (Jason Ekstrand) Reviewed-by: Jason Ekstrand <[email protected]>
* spirv: Calculate properly 16-bit vector sizesJose Maria Casanova Crespo2018-02-281-5/+2
| | | | | | | | | | | Range in 16-bit push constants load was being calculated wrongly using 4-bytes per element instead of 2-bytes as it should be. v2: Use glsl_get_bit_size instead of if statement (Jason Ekstrand) Reviewed-by: Jason Ekstrand <[email protected]>
* anv: Enable VK_KHR_16bit_storage for SSBO and UBOJose Maria Casanova Crespo2018-02-282-3/+4
| | | | | | | Enables storageBuffer16BitAccess and uniformAndStorageBuffer16BitAccesss features of VK_KHR_16bit_storage for Gen8+. Reviewed-by: Jason Ekstrand <[email protected]>
* i965/fs: Support 16-bit store_ssbo with VK_KHR_relaxed_block_layoutJose Maria Casanova Crespo2018-02-281-7/+15
| | | | | | | | | | | | | | | | Restrict the use of untyped_surface_write with 16-bit pairs in ssbo to the cases where we can guarantee that offset is multiple of 4. Taking into account that VK_KHR_relaxed_block_layout is available in ANV we can only guarantee that when we have a constant offset that is multiple of 4. For non constant offsets we will always use byte_scattered_write. v2: (Jason Ekstrand) - Assert offset_reg to be multiple of 4 if it is immediate. Reviewed-by: Jason Ekstrand <[email protected]>
* i965/fs: Support 16-bit do_read_vector with VK_KHR_relaxed_block_layoutJose Maria Casanova Crespo2018-02-281-14/+37
| | | | | | | | | | | | | | | | | | | | | | | | | | 16-bit load_ubo/ssbo operations that call do_untyped_read_vector don't guarantee that offsets are multiple of 4-bytes as required by untyped_read message. This happens for example in the case of f16mat3x3 when then VK_KHR_relaxed_block_layout is enabled. Vectors reads when we have non-constant offsets are implemented with multiple byte_scattered_read messages that not require 32-bit aligned offsets. Now for all constant offsets we can use the untyped_read_surface message. In the case of constant offsets not aligned to 32-bits, we calculate a start offset 32-bit aligned and use the shuffle_32bit_load_result_to_16bit_data function and the first_component parameter to skip the copy of the unneeded component. v2: (Jason Ekstrand) Use untyped_read_surface messages always we have constant offsets. v3: (Jason Ekstrand) Simplify loop for reads with non constant offsets. Use end - start to calculate the number of 32-bit components to read with constant offsets. Reviewed-by: Jason Ekstrand <[email protected]>
* i965/fs: shuffle_32bit_load_result_to_16bit_data now skips componentsJose Maria Casanova Crespo2018-02-283-3/+6
| | | | | | | | | | | | | | | | This helper used to load 16bit components from 32-bits read now allows skipping components with the new parameter first_component. The semantics now skip components until we reach the first_component, and then reads the number of components passed to the function. All previous uses of the helper are updated to use 0 as first_component. This will allow read 16-bit components when the first one is not aligned 32-bit. Enabling more usages of untyped_reads with 16-bit types. v2: (Jason Ektrand) Change parameters order to first_component, num_components Reviewed-by: Jason Ekstrand <[email protected]>
* isl/i965/fs: SSBO/UBO buffers need size padding if not multiple of 32-bitJose Maria Casanova Crespo2018-02-283-2/+62
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The surfaces that backup the GPU buffers have a boundary check that considers that access to partial dwords are considered out-of-bounds. For example, buffers with 1,3 16-bit elements has size 2 or 6 and the last two bytes would always be read as 0 or its writting ignored. The introduction of 16-bit types implies that we need to align the size to 4-bytew multiples so that partial dwords could be read/written. Adding an inconditional +2 size to buffers not being multiple of 2 solves this issue for the general cases of UBO or SSBO. But, when unsized arrays of 16-bit elements are used it is not possible to know if the size was padded or not. To solve this issue the implementation calculates the needed size of the buffer surfaces, as suggested by Jason: surface_size = isl_align(buffer_size, 4) + (isl_align(buffer_size, 4) - buffer_size) So when we calculate backwards the buffer_size in the backend we update the resinfo return value with: buffer_size = (surface_size & ~3) - (surface_size & 3) It is also exposed this buffer requirements when robust buffer access is enabled so these buffer sizes recommend being multiple of 4. v2: (Jason Ekstrand) Move padding logic fron anv to isl_surface_state. Move calculus of original size from spirv to driver backend. v3: (Jason Ekstrand) Rename some variables and use a similar expresion when calculating. padding than when obtaining the original buffer size. Avoid use of unnecesary component call at brw_fs_nir. v4: (Jason Ekstrand) Complete comment with buffer size calculus explanation in brw_fs_nir. Reviewed-by: Jason Ekstrand <[email protected]>
* vbo: Remove vbo_save_vertex_list::vertex_size.Mathias Fröhlich2018-03-012-9/+6
| | | | | | | | Like before use local variables from compile_vertex_list instead. Remove vertex_size from struct vbo_save_vertex_list. Reviewed-by: Brian Paul <[email protected]> Signed-off-by: Mathias Fröhlich <[email protected]>
* vbo: Remove vbo_save_vertex_list::buffer_offset.Mathias Fröhlich2018-03-012-29/+13
| | | | | | | | | | The buffer_offset is used in aligned_vertex_buffer_offset. But now that most of these decisions are done in compile_vertex_list we can work on local variables instead of struct members in the display list code. Clean that up and remove buffer_offset. Reviewed-by: Brian Paul <[email protected]> Signed-off-by: Mathias Fröhlich <[email protected]>
* vbo: Remove vbo_save_vertex_list::start_vertex.Mathias Fröhlich2018-03-013-6/+2
| | | | | | | | Replace last use on replay with _vbo_save_get_{min,max}_index. Appart from that it is not used anymore. Reviewed-by: Brian Paul <[email protected]> Signed-off-by: Mathias Fröhlich <[email protected]>
* vbo: Remove vbo_save_vertex_list::attrsz.Mathias Fröhlich2018-03-012-7/+4
| | | | | | | | Is not used anymore on replay, move the last use in display list compilation to the original array in the display list compiler. Reviewed-by: Brian Paul <[email protected]> Signed-off-by: Mathias Fröhlich <[email protected]>
* vbo: Remove vbo_save_vertex_list::attrtype.Mathias Fröhlich2018-03-012-4/+1
| | | | | | | | Is not used anymore on replay, move the last use in display list compilation to the original array in the display list compiler. Reviewed-by: Brian Paul <[email protected]> Signed-off-by: Mathias Fröhlich <[email protected]>
* vbo: Remove vbo_save_vertex_list::enabled.Mathias Fröhlich2018-03-012-3/+1
| | | | | | | Is not used anymore on replay. Reviewed-by: Brian Paul <[email protected]> Signed-off-by: Mathias Fröhlich <[email protected]>
* vbo: Remove reference to the vertex_store from the dlist node.Mathias Fröhlich2018-03-013-21/+10
| | | | | | | | Since we now store a set of VAOs in the display list, use these object to get the reference to the VBO in several places. Reviewed-by: Brian Paul <[email protected]> Signed-off-by: Mathias Fröhlich <[email protected]>
* vbo: Implement current values update in terms of the VAO.Mathias Fröhlich2018-03-013-62/+47
| | | | | | | | | Use the information already present in the VAO to update the current values after display list replay. Set GL_OUT_OF_MEMORY on allocation failure for the current value update storage. Reviewed-by: Brian Paul <[email protected]> Signed-off-by: Mathias Fröhlich <[email protected]>
* vbo: Implement vbo_loopback_vertex_list in terms of the VAO.Mathias Fröhlich2018-03-014-93/+151
| | | | | | | | | | | Use the information already present in the VAO to replay a display list node using immediate mode draw commands. Use a hand full of helper methods that will be useful for the next patches also. v2: Insert asserts, constify local variables. Reviewed-by: Brian Paul <[email protected]> Signed-off-by: Mathias Fröhlich <[email protected]>
generated by cgit v1.2.3 (git 2.39.1) at 2024-12-04 16:31:38 +0000