diff options
Diffstat (limited to 'src')
| -rw-r--r-- | src/amd/common/ac_gpu_info.c | 55 | ||||
| -rw-r--r-- | src/amd/common/ac_gpu_info.h | 1 | ||||
| -rw-r--r-- | src/gallium/drivers/radeon/r600_pipe_common.c | 154 | ||||
| -rw-r--r-- | src/gallium/drivers/radeon/r600_pipe_common.h | 3 | ||||
| -rw-r--r-- | src/gallium/drivers/radeonsi/si_pipe.c | 101 |
5 files changed, 154 insertions, 160 deletions
diff --git a/src/amd/common/ac_gpu_info.c b/src/amd/common/ac_gpu_info.c index 6e34a070132..0576dd369cf 100644 --- a/src/amd/common/ac_gpu_info.c +++ b/src/amd/common/ac_gpu_info.c @@ -353,3 +353,58 @@ void ac_compute_device_uuid(struct radeon_info *info, char *uuid, size_t size) uint_uuid[2] = info->pci_dev; uint_uuid[3] = info->pci_func; } + +void ac_print_gpu_info(struct radeon_info *info) +{ + printf("pci (domain:bus:dev.func): %04x:%02x:%02x.%x\n", + info->pci_domain, info->pci_bus, + info->pci_dev, info->pci_func); + printf("pci_id = 0x%x\n", info->pci_id); + printf("family = %i\n", info->family); + printf("chip_class = %i\n", info->chip_class); + printf("pte_fragment_size = %u\n", info->pte_fragment_size); + printf("gart_page_size = %u\n", info->gart_page_size); + printf("gart_size = %i MB\n", (int)DIV_ROUND_UP(info->gart_size, 1024*1024)); + printf("vram_size = %i MB\n", (int)DIV_ROUND_UP(info->vram_size, 1024*1024)); + printf("vram_vis_size = %i MB\n", (int)DIV_ROUND_UP(info->vram_vis_size, 1024*1024)); + printf("max_alloc_size = %i MB\n", + (int)DIV_ROUND_UP(info->max_alloc_size, 1024*1024)); + printf("min_alloc_size = %u\n", info->min_alloc_size); + printf("has_dedicated_vram = %u\n", info->has_dedicated_vram); + printf("has_virtual_memory = %i\n", info->has_virtual_memory); + printf("gfx_ib_pad_with_type2 = %i\n", info->gfx_ib_pad_with_type2); + printf("has_hw_decode = %u\n", info->has_hw_decode); + printf("num_sdma_rings = %i\n", info->num_sdma_rings); + printf("num_compute_rings = %u\n", info->num_compute_rings); + printf("uvd_fw_version = %u\n", info->uvd_fw_version); + printf("vce_fw_version = %u\n", info->vce_fw_version); + printf("me_fw_version = %i\n", info->me_fw_version); + printf("me_fw_feature = %i\n", info->me_fw_feature); + printf("pfp_fw_version = %i\n", info->pfp_fw_version); + printf("pfp_fw_feature = %i\n", info->pfp_fw_feature); + printf("ce_fw_version = %i\n", info->ce_fw_version); + printf("ce_fw_feature = %i\n", info->ce_fw_feature); + printf("vce_harvest_config = %i\n", info->vce_harvest_config); + printf("clock_crystal_freq = %i\n", info->clock_crystal_freq); + printf("tcc_cache_line_size = %u\n", info->tcc_cache_line_size); + printf("drm = %i.%i.%i\n", info->drm_major, + info->drm_minor, info->drm_patchlevel); + printf("has_userptr = %i\n", info->has_userptr); + printf("has_syncobj = %u\n", info->has_syncobj); + printf("has_sync_file = %u\n", info->has_sync_file); + + printf("r600_max_quad_pipes = %i\n", info->r600_max_quad_pipes); + printf("max_shader_clock = %i\n", info->max_shader_clock); + printf("num_good_compute_units = %i\n", info->num_good_compute_units); + printf("max_se = %i\n", info->max_se); + printf("max_sh_per_se = %i\n", info->max_sh_per_se); + + printf("r600_gb_backend_map = %i\n", info->r600_gb_backend_map); + printf("r600_gb_backend_map_valid = %i\n", info->r600_gb_backend_map_valid); + printf("r600_num_banks = %i\n", info->r600_num_banks); + printf("num_render_backends = %i\n", info->num_render_backends); + printf("num_tile_pipes = %i\n", info->num_tile_pipes); + printf("pipe_interleave_bytes = %i\n", info->pipe_interleave_bytes); + printf("enabled_rb_mask = 0x%x\n", info->enabled_rb_mask); + printf("max_alignment = %u\n", (unsigned)info->max_alignment); +} diff --git a/src/amd/common/ac_gpu_info.h b/src/amd/common/ac_gpu_info.h index 92c94f046b5..5b9e51658b0 100644 --- a/src/amd/common/ac_gpu_info.h +++ b/src/amd/common/ac_gpu_info.h @@ -115,6 +115,7 @@ bool ac_query_gpu_info(int fd, amdgpu_device_handle dev, void ac_compute_driver_uuid(char *uuid, size_t size); void ac_compute_device_uuid(struct radeon_info *info, char *uuid, size_t size); +void ac_print_gpu_info(struct radeon_info *info); #ifdef __cplusplus } diff --git a/src/gallium/drivers/radeon/r600_pipe_common.c b/src/gallium/drivers/radeon/r600_pipe_common.c index 60e549090a8..069594f9f22 100644 --- a/src/gallium/drivers/radeon/r600_pipe_common.c +++ b/src/gallium/drivers/radeon/r600_pipe_common.c @@ -510,160 +510,6 @@ void si_common_context_cleanup(struct r600_common_context *rctx) r600_resource_reference(&rctx->eop_bug_scratch, NULL); } -/* - * pipe_screen - */ - -static const struct debug_named_value common_debug_options[] = { - /* logging */ - { "tex", DBG(TEX), "Print texture info" }, - { "nir", DBG(NIR), "Enable experimental NIR shaders" }, - { "compute", DBG(COMPUTE), "Print compute info" }, - { "vm", DBG(VM), "Print virtual addresses when creating resources" }, - { "info", DBG(INFO), "Print driver information" }, - - /* shaders */ - { "vs", DBG(VS), "Print vertex shaders" }, - { "gs", DBG(GS), "Print geometry shaders" }, - { "ps", DBG(PS), "Print pixel shaders" }, - { "cs", DBG(CS), "Print compute shaders" }, - { "tcs", DBG(TCS), "Print tessellation control shaders" }, - { "tes", DBG(TES), "Print tessellation evaluation shaders" }, - { "noir", DBG(NO_IR), "Don't print the LLVM IR"}, - { "notgsi", DBG(NO_TGSI), "Don't print the TGSI"}, - { "noasm", DBG(NO_ASM), "Don't print disassembled shaders"}, - { "preoptir", DBG(PREOPT_IR), "Print the LLVM IR before initial optimizations" }, - { "checkir", DBG(CHECK_IR), "Enable additional sanity checks on shader IR" }, - { "nooptvariant", DBG(NO_OPT_VARIANT), "Disable compiling optimized shader variants." }, - - { "testdma", DBG(TEST_DMA), "Invoke SDMA tests and exit." }, - { "testvmfaultcp", DBG(TEST_VMFAULT_CP), "Invoke a CP VM fault test and exit." }, - { "testvmfaultsdma", DBG(TEST_VMFAULT_SDMA), "Invoke a SDMA VM fault test and exit." }, - { "testvmfaultshader", DBG(TEST_VMFAULT_SHADER), "Invoke a shader VM fault test and exit." }, - - /* features */ - { "nodma", DBG(NO_ASYNC_DMA), "Disable asynchronous DMA" }, - { "nohyperz", DBG(NO_HYPERZ), "Disable Hyper-Z" }, - { "no2d", DBG(NO_2D_TILING), "Disable 2D tiling" }, - { "notiling", DBG(NO_TILING), "Disable tiling" }, - { "switch_on_eop", DBG(SWITCH_ON_EOP), "Program WD/IA to switch on end-of-packet." }, - { "forcedma", DBG(FORCE_DMA), "Use asynchronous DMA for all operations when possible." }, - { "precompile", DBG(PRECOMPILE), "Compile one shader variant at shader creation." }, - { "nowc", DBG(NO_WC), "Disable GTT write combining" }, - { "check_vm", DBG(CHECK_VM), "Check VM faults and dump debug info." }, - { "nodcc", DBG(NO_DCC), "Disable DCC." }, - { "nodccclear", DBG(NO_DCC_CLEAR), "Disable DCC fast clear." }, - { "norbplus", DBG(NO_RB_PLUS), "Disable RB+." }, - { "sisched", DBG(SI_SCHED), "Enable LLVM SI Machine Instruction Scheduler." }, - { "mono", DBG(MONOLITHIC_SHADERS), "Use old-style monolithic shaders compiled on demand" }, - { "unsafemath", DBG(UNSAFE_MATH), "Enable unsafe math shader optimizations" }, - { "nodccfb", DBG(NO_DCC_FB), "Disable separate DCC on the main framebuffer" }, - { "nodccmsaa", DBG(NO_DCC_MSAA), "Disable DCC for MSAA" }, - { "dccmsaa", DBG(DCC_MSAA), "Enable DCC for MSAA" }, - { "nodpbb", DBG(NO_DPBB), "Disable DPBB." }, - { "nodfsm", DBG(NO_DFSM), "Disable DFSM." }, - { "dpbb", DBG(DPBB), "Enable DPBB." }, - { "dfsm", DBG(DFSM), "Enable DFSM." }, - { "nooutoforder", DBG(NO_OUT_OF_ORDER), "Disable out-of-order rasterization" }, - { "reserve_vmid", DBG(RESERVE_VMID), "Force VMID reservation per context." }, - - DEBUG_NAMED_VALUE_END /* must be last */ -}; - -bool si_common_screen_init(struct r600_common_screen *rscreen, - struct radeon_winsys *ws) -{ - si_init_screen_texture_functions(rscreen); - si_init_screen_query_functions(rscreen); - - rscreen->debug_flags |= debug_get_flags_option("R600_DEBUG", common_debug_options, 0); - rscreen->has_rbplus = false; - rscreen->rbplus_allowed = false; - - slab_create_parent(&rscreen->pool_transfers, sizeof(struct r600_transfer), 64); - - rscreen->force_aniso = MIN2(16, debug_get_num_option("R600_TEX_ANISO", -1)); - if (rscreen->force_aniso >= 0) { - printf("radeon: Forcing anisotropy filter to %ix\n", - /* round down to a power of two */ - 1 << util_logbase2(rscreen->force_aniso)); - } - - (void) mtx_init(&rscreen->aux_context_lock, mtx_plain); - (void) mtx_init(&rscreen->gpu_load_mutex, mtx_plain); - - if (rscreen->debug_flags & DBG(INFO)) { - printf("pci (domain:bus:dev.func): %04x:%02x:%02x.%x\n", - rscreen->info.pci_domain, rscreen->info.pci_bus, - rscreen->info.pci_dev, rscreen->info.pci_func); - printf("pci_id = 0x%x\n", rscreen->info.pci_id); - printf("family = %i\n", rscreen->info.family); - printf("chip_class = %i\n", rscreen->info.chip_class); - printf("pte_fragment_size = %u\n", rscreen->info.pte_fragment_size); - printf("gart_page_size = %u\n", rscreen->info.gart_page_size); - printf("gart_size = %i MB\n", (int)DIV_ROUND_UP(rscreen->info.gart_size, 1024*1024)); - printf("vram_size = %i MB\n", (int)DIV_ROUND_UP(rscreen->info.vram_size, 1024*1024)); - printf("vram_vis_size = %i MB\n", (int)DIV_ROUND_UP(rscreen->info.vram_vis_size, 1024*1024)); - printf("max_alloc_size = %i MB\n", - (int)DIV_ROUND_UP(rscreen->info.max_alloc_size, 1024*1024)); - printf("min_alloc_size = %u\n", rscreen->info.min_alloc_size); - printf("has_dedicated_vram = %u\n", rscreen->info.has_dedicated_vram); - printf("has_virtual_memory = %i\n", rscreen->info.has_virtual_memory); - printf("gfx_ib_pad_with_type2 = %i\n", rscreen->info.gfx_ib_pad_with_type2); - printf("has_hw_decode = %u\n", rscreen->info.has_hw_decode); - printf("num_sdma_rings = %i\n", rscreen->info.num_sdma_rings); - printf("num_compute_rings = %u\n", rscreen->info.num_compute_rings); - printf("uvd_fw_version = %u\n", rscreen->info.uvd_fw_version); - printf("vce_fw_version = %u\n", rscreen->info.vce_fw_version); - printf("me_fw_version = %i\n", rscreen->info.me_fw_version); - printf("me_fw_feature = %i\n", rscreen->info.me_fw_feature); - printf("pfp_fw_version = %i\n", rscreen->info.pfp_fw_version); - printf("pfp_fw_feature = %i\n", rscreen->info.pfp_fw_feature); - printf("ce_fw_version = %i\n", rscreen->info.ce_fw_version); - printf("ce_fw_feature = %i\n", rscreen->info.ce_fw_feature); - printf("vce_harvest_config = %i\n", rscreen->info.vce_harvest_config); - printf("clock_crystal_freq = %i\n", rscreen->info.clock_crystal_freq); - printf("tcc_cache_line_size = %u\n", rscreen->info.tcc_cache_line_size); - printf("drm = %i.%i.%i\n", rscreen->info.drm_major, - rscreen->info.drm_minor, rscreen->info.drm_patchlevel); - printf("has_userptr = %i\n", rscreen->info.has_userptr); - printf("has_syncobj = %u\n", rscreen->info.has_syncobj); - printf("has_sync_file = %u\n", rscreen->info.has_sync_file); - - printf("r600_max_quad_pipes = %i\n", rscreen->info.r600_max_quad_pipes); - printf("max_shader_clock = %i\n", rscreen->info.max_shader_clock); - printf("num_good_compute_units = %i\n", rscreen->info.num_good_compute_units); - printf("max_se = %i\n", rscreen->info.max_se); - printf("max_sh_per_se = %i\n", rscreen->info.max_sh_per_se); - - printf("r600_gb_backend_map = %i\n", rscreen->info.r600_gb_backend_map); - printf("r600_gb_backend_map_valid = %i\n", rscreen->info.r600_gb_backend_map_valid); - printf("r600_num_banks = %i\n", rscreen->info.r600_num_banks); - printf("num_render_backends = %i\n", rscreen->info.num_render_backends); - printf("num_tile_pipes = %i\n", rscreen->info.num_tile_pipes); - printf("pipe_interleave_bytes = %i\n", rscreen->info.pipe_interleave_bytes); - printf("enabled_rb_mask = 0x%x\n", rscreen->info.enabled_rb_mask); - printf("max_alignment = %u\n", (unsigned)rscreen->info.max_alignment); - } - return true; -} - -void si_destroy_common_screen(struct r600_common_screen *rscreen) -{ - si_perfcounters_destroy(rscreen); - si_gpu_load_kill_thread(rscreen); - - mtx_destroy(&rscreen->gpu_load_mutex); - mtx_destroy(&rscreen->aux_context_lock); - rscreen->aux_context->destroy(rscreen->aux_context); - - slab_destroy_parent(&rscreen->pool_transfers); - - disk_cache_destroy(rscreen->disk_shader_cache); - rscreen->ws->destroy(rscreen->ws); - FREE(rscreen); -} - bool si_can_dump_shader(struct r600_common_screen *rscreen, unsigned processor) { diff --git a/src/gallium/drivers/radeon/r600_pipe_common.h b/src/gallium/drivers/radeon/r600_pipe_common.h index 769024e83f3..2f8dc9065ae 100644 --- a/src/gallium/drivers/radeon/r600_pipe_common.h +++ b/src/gallium/drivers/radeon/r600_pipe_common.h @@ -639,9 +639,6 @@ void si_gfx_write_event_eop(struct r600_common_context *ctx, unsigned si_gfx_write_fence_dwords(struct r600_common_screen *screen); void si_gfx_wait_fence(struct r600_common_context *ctx, uint64_t va, uint32_t ref, uint32_t mask); -bool si_common_screen_init(struct r600_common_screen *rscreen, - struct radeon_winsys *ws); -void si_destroy_common_screen(struct r600_common_screen *rscreen); bool si_common_context_init(struct r600_common_context *rctx, struct r600_common_screen *rscreen, unsigned context_flags); diff --git a/src/gallium/drivers/radeonsi/si_pipe.c b/src/gallium/drivers/radeonsi/si_pipe.c index af521a203ae..141662ac2cf 100644 --- a/src/gallium/drivers/radeonsi/si_pipe.c +++ b/src/gallium/drivers/radeonsi/si_pipe.c @@ -36,6 +36,69 @@ #include "vl/vl_decoder.h" #include "../ddebug/dd_util.h" +static const struct debug_named_value debug_options[] = { + /* Shader logging options: */ + { "vs", DBG(VS), "Print vertex shaders" }, + { "ps", DBG(PS), "Print pixel shaders" }, + { "gs", DBG(GS), "Print geometry shaders" }, + { "tcs", DBG(TCS), "Print tessellation control shaders" }, + { "tes", DBG(TES), "Print tessellation evaluation shaders" }, + { "cs", DBG(CS), "Print compute shaders" }, + { "noir", DBG(NO_IR), "Don't print the LLVM IR"}, + { "notgsi", DBG(NO_TGSI), "Don't print the TGSI"}, + { "noasm", DBG(NO_ASM), "Don't print disassembled shaders"}, + { "preoptir", DBG(PREOPT_IR), "Print the LLVM IR before initial optimizations" }, + + /* Shader compiler options the shader cache should be aware of: */ + { "unsafemath", DBG(UNSAFE_MATH), "Enable unsafe math shader optimizations" }, + { "sisched", DBG(SI_SCHED), "Enable LLVM SI Machine Instruction Scheduler." }, + + /* Shader compiler options (with no effect on the shader cache): */ + { "checkir", DBG(CHECK_IR), "Enable additional sanity checks on shader IR" }, + { "precompile", DBG(PRECOMPILE), "Compile one shader variant at shader creation." }, + { "nir", DBG(NIR), "Enable experimental NIR shaders" }, + { "mono", DBG(MONOLITHIC_SHADERS), "Use old-style monolithic shaders compiled on demand" }, + { "nooptvariant", DBG(NO_OPT_VARIANT), "Disable compiling optimized shader variants." }, + + /* Information logging options: */ + { "info", DBG(INFO), "Print driver information" }, + { "tex", DBG(TEX), "Print texture info" }, + { "compute", DBG(COMPUTE), "Print compute info" }, + { "vm", DBG(VM), "Print virtual addresses when creating resources" }, + + /* Driver options: */ + { "forcedma", DBG(FORCE_DMA), "Use asynchronous DMA for all operations when possible." }, + { "nodma", DBG(NO_ASYNC_DMA), "Disable asynchronous DMA" }, + { "nowc", DBG(NO_WC), "Disable GTT write combining" }, + { "check_vm", DBG(CHECK_VM), "Check VM faults and dump debug info." }, + { "reserve_vmid", DBG(RESERVE_VMID), "Force VMID reservation per context." }, + + /* 3D engine options: */ + { "switch_on_eop", DBG(SWITCH_ON_EOP), "Program WD/IA to switch on end-of-packet." }, + { "nooutoforder", DBG(NO_OUT_OF_ORDER), "Disable out-of-order rasterization" }, + { "nodpbb", DBG(NO_DPBB), "Disable DPBB." }, + { "nodfsm", DBG(NO_DFSM), "Disable DFSM." }, + { "dpbb", DBG(DPBB), "Enable DPBB." }, + { "dfsm", DBG(DFSM), "Enable DFSM." }, + { "nohyperz", DBG(NO_HYPERZ), "Disable Hyper-Z" }, + { "norbplus", DBG(NO_RB_PLUS), "Disable RB+." }, + { "no2d", DBG(NO_2D_TILING), "Disable 2D tiling" }, + { "notiling", DBG(NO_TILING), "Disable tiling" }, + { "nodcc", DBG(NO_DCC), "Disable DCC." }, + { "nodccclear", DBG(NO_DCC_CLEAR), "Disable DCC fast clear." }, + { "nodccfb", DBG(NO_DCC_FB), "Disable separate DCC on the main framebuffer" }, + { "nodccmsaa", DBG(NO_DCC_MSAA), "Disable DCC for MSAA" }, + { "dccmsaa", DBG(DCC_MSAA), "Enable DCC for MSAA" }, + + /* Tests: */ + { "testdma", DBG(TEST_DMA), "Invoke SDMA tests and exit." }, + { "testvmfaultcp", DBG(TEST_VMFAULT_CP), "Invoke a CP VM fault test and exit." }, + { "testvmfaultsdma", DBG(TEST_VMFAULT_SDMA), "Invoke a SDMA VM fault test and exit." }, + { "testvmfaultshader", DBG(TEST_VMFAULT_SHADER), "Invoke a shader VM fault test and exit." }, + + DEBUG_NAMED_VALUE_END /* must be last */ +}; + /* * pipe_context */ @@ -440,7 +503,19 @@ static void si_destroy_screen(struct pipe_screen* pscreen) } mtx_destroy(&sscreen->shader_parts_mutex); si_destroy_shader_cache(sscreen); - si_destroy_common_screen(&sscreen->b); + + si_perfcounters_destroy(&sscreen->b); + si_gpu_load_kill_thread(&sscreen->b); + + mtx_destroy(&sscreen->b.gpu_load_mutex); + mtx_destroy(&sscreen->b.aux_context_lock); + sscreen->b.aux_context->destroy(sscreen->b.aux_context); + + slab_destroy_parent(&sscreen->b.pool_transfers); + + disk_cache_destroy(sscreen->b.disk_shader_cache); + sscreen->b.ws->destroy(sscreen->b.ws); + FREE(sscreen); } static bool si_init_gs_info(struct si_screen *sscreen) @@ -595,6 +670,8 @@ struct pipe_screen *radeonsi_screen_create(struct radeon_winsys *ws, sscreen->b.family = sscreen->b.info.family; sscreen->b.chip_class = sscreen->b.info.chip_class; + sscreen->b.debug_flags = debug_get_flags_option("R600_DEBUG", + debug_options, 0); /* Set functions first. */ sscreen->b.b.context_create = si_pipe_create_context; @@ -604,6 +681,8 @@ struct pipe_screen *radeonsi_screen_create(struct radeon_winsys *ws, si_init_screen_buffer_functions(sscreen); si_init_screen_fence_functions(sscreen); si_init_screen_state_functions(sscreen); + si_init_screen_texture_functions(&sscreen->b); + si_init_screen_query_functions(&sscreen->b); /* Set these flags in debug_flags early, so that the shader cache takes * them into account. @@ -614,8 +693,24 @@ struct pipe_screen *radeonsi_screen_create(struct radeon_winsys *ws, if (driQueryOptionb(config->options, "radeonsi_enable_sisched")) sscreen->b.debug_flags |= DBG(SI_SCHED); - if (!si_common_screen_init(&sscreen->b, ws) || - !si_init_gs_info(sscreen) || + + if (sscreen->b.debug_flags & DBG(INFO)) + ac_print_gpu_info(&sscreen->b.info); + + slab_create_parent(&sscreen->b.pool_transfers, + sizeof(struct r600_transfer), 64); + + sscreen->b.force_aniso = MIN2(16, debug_get_num_option("R600_TEX_ANISO", -1)); + if (sscreen->b.force_aniso >= 0) { + printf("radeonsi: Forcing anisotropy filter to %ix\n", + /* round down to a power of two */ + 1 << util_logbase2(sscreen->b.force_aniso)); + } + + (void) mtx_init(&sscreen->b.aux_context_lock, mtx_plain); + (void) mtx_init(&sscreen->b.gpu_load_mutex, mtx_plain); + + if (!si_init_gs_info(sscreen) || !si_init_shader_cache(sscreen)) { FREE(sscreen); return NULL; |