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-rw-r--r--src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp17
1 files changed, 8 insertions, 9 deletions
diff --git a/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp b/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp
index 15a6cbdd256..daf46b6ab82 100644
--- a/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp
+++ b/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp
@@ -2363,10 +2363,16 @@ vec4_visitor::visit(ir_texture *ir)
assert(!"Unrecognized tex op");
}
- bool use_texture_offset = ir->offset != NULL && ir->op != ir_txf;
+ if (ir->offset != NULL && ir->op != ir_txf)
+ inst->texture_offset = brw_texture_offset(ctx, ir->offset->as_constant());
+
+ /* Stuff the channel select bits in the top of the texture offset */
+ if (ir->op == ir_tg4)
+ inst->texture_offset |= gather_channel(ir, sampler) << 16;
/* Texel offsets go in the message header; Gen4 also requires headers. */
- inst->header_present = use_texture_offset || brw->gen < 5 || ir->op == ir_tg4;
+ inst->header_present =
+ brw->gen < 5 || inst->texture_offset != 0 || ir->op == ir_tg4;
inst->base_mrf = 2;
inst->mlen = inst->header_present + 1; /* always at least one */
inst->sampler = sampler;
@@ -2374,13 +2380,6 @@ vec4_visitor::visit(ir_texture *ir)
inst->dst.writemask = WRITEMASK_XYZW;
inst->shadow_compare = ir->shadow_comparitor != NULL;
- if (use_texture_offset)
- inst->texture_offset = brw_texture_offset(ctx, ir->offset->as_constant());
-
- /* Stuff the channel select bits in the top of the texture offset */
- if (ir->op == ir_tg4)
- inst->texture_offset |= gather_channel(ir, sampler)<<16;
-
/* MRF for the first parameter */
int param_base = inst->base_mrf + inst->header_present;