diff options
Diffstat (limited to 'src')
| -rw-r--r-- | src/mesa/drivers/dri/i965/brw_blorp.c | 4 | ||||
| -rw-r--r-- | src/mesa/drivers/dri/i965/brw_state.h | 7 | ||||
| -rw-r--r-- | src/mesa/drivers/dri/i965/brw_wm_surface_state.c | 2 | ||||
| -rw-r--r-- | src/mesa/drivers/dri/i965/gen8_blorp.c | 43 |
4 files changed, 8 insertions, 48 deletions
diff --git a/src/mesa/drivers/dri/i965/brw_blorp.c b/src/mesa/drivers/dri/i965/brw_blorp.c index 215f76507f5..f66ed4670c5 100644 --- a/src/mesa/drivers/dri/i965/brw_blorp.c +++ b/src/mesa/drivers/dri/i965/brw_blorp.c @@ -344,7 +344,9 @@ brw_blorp_emit_surface_state(struct brw_context *brw, const struct isl_surf *aux_surf = NULL; uint64_t aux_offset = 0; - if (surface->mt->mcs_mt) { + if (surface->mt->mcs_mt && + (is_render_target || + surface->mt->fast_clear_state != INTEL_FAST_CLEAR_STATE_RESOLVED)) { aux_surf = &surface->aux_surf; assert(surface->mt->mcs_mt->offset == 0); aux_offset = surface->mt->mcs_mt->bo->offset64; diff --git a/src/mesa/drivers/dri/i965/brw_state.h b/src/mesa/drivers/dri/i965/brw_state.h index 81f874dea1c..fc66593442b 100644 --- a/src/mesa/drivers/dri/i965/brw_state.h +++ b/src/mesa/drivers/dri/i965/brw_state.h @@ -274,13 +274,6 @@ GLuint translate_tex_format(struct brw_context *brw, int brw_get_texture_swizzle(const struct gl_context *ctx, const struct gl_texture_object *t); -void brw_emit_surface_state(struct brw_context *brw, - struct intel_mipmap_tree *mt, - const struct isl_view *view, - uint32_t mocs, bool for_gather, - uint32_t *surf_offset, int surf_index, - unsigned read_domains, unsigned write_domains); - void brw_emit_buffer_surface_state(struct brw_context *brw, uint32_t *out_offset, drm_intel_bo *bo, diff --git a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c index a53f9da2498..9f340ef92de 100644 --- a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c +++ b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c @@ -71,7 +71,7 @@ static const struct surface_state_info surface_state_infos[] = { [9] = {16, 64, 8, 10, SKL_MOCS_WB, SKL_MOCS_PTE}, }; -void +static void brw_emit_surface_state(struct brw_context *brw, struct intel_mipmap_tree *mt, const struct isl_view *view, diff --git a/src/mesa/drivers/dri/i965/gen8_blorp.c b/src/mesa/drivers/dri/i965/gen8_blorp.c index b4dedf92982..1756b29286b 100644 --- a/src/mesa/drivers/dri/i965/gen8_blorp.c +++ b/src/mesa/drivers/dri/i965/gen8_blorp.c @@ -490,45 +490,10 @@ gen8_blorp_emit_surface_states(struct brw_context *brw, I915_GEM_DOMAIN_RENDER, true /* is_render_target */); if (params->src.mt) { - const struct brw_blorp_surface_info *surface = ¶ms->src; - struct intel_mipmap_tree *mt = surface->mt; - - /* If src is a 2D multisample array texture on Gen7+ using - * INTEL_MSAA_LAYOUT_UMS or INTEL_MSAA_LAYOUT_CMS, src layer is the - * physical layer holding sample 0. So, for example, if mt->num_samples - * == 4, then logical layer n corresponds to layer == 4*n. - * - * Multisampled depth and stencil surfaces have the samples interleaved - * (INTEL_MSAA_LAYOUT_IMS) and therefore the layer doesn't need - * adjustment. - */ - const unsigned layer_divider = - (mt->msaa_layout == INTEL_MSAA_LAYOUT_UMS || - mt->msaa_layout == INTEL_MSAA_LAYOUT_CMS) ? - MAX2(mt->num_samples, 1) : 1; - - const unsigned layer = mt->target != GL_TEXTURE_3D ? - surface->layer / layer_divider : 0; - - struct isl_view view = { - .format = surface->view.format, - .base_level = surface->level, - .levels = mt->last_level - surface->level + 1, - .base_array_layer = layer, - .array_len = mt->logical_depth0 - layer, - .channel_select = { - surface->view.channel_select[0], - surface->view.channel_select[1], - surface->view.channel_select[2], - surface->view.channel_select[3], - }, - .usage = ISL_SURF_USAGE_TEXTURE_BIT, - }; - - brw_emit_surface_state(brw, mt, &view, - brw->gen >= 9 ? SKL_MOCS_WB : BDW_MOCS_WB, - false, &wm_surf_offset_texture, -1, - I915_GEM_DOMAIN_SAMPLER, 0); + wm_surf_offset_texture = + brw_blorp_emit_surface_state(brw, ¶ms->src, + I915_GEM_DOMAIN_SAMPLER, 0, + false /* is_render_target */); } return gen6_blorp_emit_binding_table(brw, |