diff options
Diffstat (limited to 'src')
| -rw-r--r-- | src/freedreno/ir3/ir3.h | 2 | ||||
| -rw-r--r-- | src/freedreno/ir3/ir3_compiler_nir.c | 2 | ||||
| -rw-r--r-- | src/freedreno/ir3/ir3_legalize.c | 5 | ||||
| -rw-r--r-- | src/freedreno/ir3/ir3_shader.h | 3 | ||||
| -rw-r--r-- | src/gallium/drivers/freedreno/a6xx/fd6_compute.c | 2 | ||||
| -rw-r--r-- | src/gallium/drivers/freedreno/a6xx/fd6_program.c | 4 |
6 files changed, 12 insertions, 6 deletions
diff --git a/src/freedreno/ir3/ir3.h b/src/freedreno/ir3/ir3.h index 245320fe2fd..6e30f74d4ab 100644 --- a/src/freedreno/ir3/ir3.h +++ b/src/freedreno/ir3/ir3.h @@ -1028,7 +1028,7 @@ int ir3_ra(struct ir3 *ir3, gl_shader_stage type, bool frag_coord, bool frag_face); /* legalize: */ -void ir3_legalize(struct ir3 *ir, bool *has_ssbo, int *max_bary); +void ir3_legalize(struct ir3 *ir, bool *has_ssbo, bool *need_pixlod, int *max_bary); /* ************************************************************************* */ /* instruction helpers */ diff --git a/src/freedreno/ir3/ir3_compiler_nir.c b/src/freedreno/ir3/ir3_compiler_nir.c index 402da13792b..57a8758140b 100644 --- a/src/freedreno/ir3/ir3_compiler_nir.c +++ b/src/freedreno/ir3/ir3_compiler_nir.c @@ -2798,7 +2798,7 @@ ir3_compile_shader_nir(struct ir3_compiler *compiler, /* We need to do legalize after (for frag shader's) the "bary.f" * offsets (inloc) have been assigned. */ - ir3_legalize(ir, &so->has_ssbo, &max_bary); + ir3_legalize(ir, &so->has_ssbo, &so->need_pixlod, &max_bary); if (ir3_shader_debug & IR3_DBG_OPTMSGS) { printf("AFTER LEGALIZE:\n"); diff --git a/src/freedreno/ir3/ir3_legalize.c b/src/freedreno/ir3/ir3_legalize.c index f015c6fede8..cb9a3f97292 100644 --- a/src/freedreno/ir3/ir3_legalize.c +++ b/src/freedreno/ir3/ir3_legalize.c @@ -42,6 +42,7 @@ struct ir3_legalize_ctx { struct ir3_compiler *compiler; bool has_ssbo; + bool need_pixlod; int max_bary; }; @@ -218,6 +219,7 @@ legalize_block(struct ir3_legalize_ctx *ctx, struct ir3_block *block) if (is_tex(n)) { regmask_set(&state->needs_sy, n->regs[0]); + ctx->need_pixlod = true; } else if (n->opc == OPC_RESINFO) { regmask_set(&state->needs_ss, n->regs[0]); ir3_NOP(block)->flags |= IR3_INSTR_SS; @@ -471,7 +473,7 @@ mark_convergence_points(struct ir3 *ir) } void -ir3_legalize(struct ir3 *ir, bool *has_ssbo, int *max_bary) +ir3_legalize(struct ir3 *ir, bool *has_ssbo, bool *need_pixlod, int *max_bary) { struct ir3_legalize_ctx *ctx = rzalloc(ir, struct ir3_legalize_ctx); bool progress; @@ -493,6 +495,7 @@ ir3_legalize(struct ir3 *ir, bool *has_ssbo, int *max_bary) } while (progress); *has_ssbo = ctx->has_ssbo; + *need_pixlod = ctx->need_pixlod; *max_bary = ctx->max_bary; do { diff --git a/src/freedreno/ir3/ir3_shader.h b/src/freedreno/ir3/ir3_shader.h index d598dd76eee..647651c03b0 100644 --- a/src/freedreno/ir3/ir3_shader.h +++ b/src/freedreno/ir3/ir3_shader.h @@ -431,6 +431,9 @@ struct ir3_shader_variant { /* do we have one or more SSBO instructions: */ bool has_ssbo; + /* do we need derivatives: */ + bool need_pixlod; + /* do we have kill, image write, etc (which prevents early-z): */ bool no_earlyz; diff --git a/src/gallium/drivers/freedreno/a6xx/fd6_compute.c b/src/gallium/drivers/freedreno/a6xx/fd6_compute.c index 1219d7ad9b3..f3bc0ed231d 100644 --- a/src/gallium/drivers/freedreno/a6xx/fd6_compute.c +++ b/src/gallium/drivers/freedreno/a6xx/fd6_compute.c @@ -96,7 +96,7 @@ cs_program_emit(struct fd_ringbuffer *ring, struct ir3_shader_variant *v, A6XX_SP_CS_CTRL_REG0_FULLREGFOOTPRINT(i->max_reg + 1) | A6XX_SP_CS_CTRL_REG0_MERGEDREGS | A6XX_SP_CS_CTRL_REG0_BRANCHSTACK(v->branchstack) | - COND(v->num_samp > 0, A6XX_SP_CS_CTRL_REG0_PIXLODENABLE)); + COND(v->need_pixlod, A6XX_SP_CS_CTRL_REG0_PIXLODENABLE)); OUT_PKT4(ring, REG_A6XX_SP_CS_UNKNOWN_A9B1, 1); OUT_RING(ring, 0x41); diff --git a/src/gallium/drivers/freedreno/a6xx/fd6_program.c b/src/gallium/drivers/freedreno/a6xx/fd6_program.c index 668b10cccc9..c20472f63c2 100644 --- a/src/gallium/drivers/freedreno/a6xx/fd6_program.c +++ b/src/gallium/drivers/freedreno/a6xx/fd6_program.c @@ -396,7 +396,7 @@ setup_stateobj(struct fd_ringbuffer *ring, A6XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT(s[VS].i->max_reg + 1) | A6XX_SP_VS_CTRL_REG0_MERGEDREGS | A6XX_SP_VS_CTRL_REG0_BRANCHSTACK(s[VS].v->branchstack) | - COND(s[VS].v->num_samp > 0, A6XX_SP_VS_CTRL_REG0_PIXLODENABLE)); + COND(s[VS].v->need_pixlod, A6XX_SP_VS_CTRL_REG0_PIXLODENABLE)); struct ir3_shader_linkage l = {0}; ir3_link_shaders(&l, s[VS].v, s[FS].v); @@ -518,7 +518,7 @@ setup_stateobj(struct fd_ringbuffer *ring, A6XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT(s[FS].i->max_reg + 1) | A6XX_SP_FS_CTRL_REG0_MERGEDREGS | A6XX_SP_FS_CTRL_REG0_BRANCHSTACK(s[FS].v->branchstack) | - COND(s[FS].v->num_samp > 0, A6XX_SP_FS_CTRL_REG0_PIXLODENABLE)); + COND(s[FS].v->need_pixlod, A6XX_SP_FS_CTRL_REG0_PIXLODENABLE)); OUT_PKT4(ring, REG_A6XX_SP_UNKNOWN_A982, 1); OUT_RING(ring, 0); /* XXX */ |