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-rw-r--r--src/mesa/drivers/dri/i965/Makefile.sources1
-rw-r--r--src/mesa/drivers/dri/i965/brw_misc_state.c46
-rw-r--r--src/mesa/drivers/dri/i965/brw_state.h7
-rw-r--r--src/mesa/drivers/dri/i965/brw_state_upload.c4
-rw-r--r--src/mesa/drivers/dri/i965/gen6_blorp.c2
-rw-r--r--src/mesa/drivers/dri/i965/gen7_blorp.c2
-rw-r--r--src/mesa/drivers/dri/i965/gen8_blorp.c4
-rw-r--r--src/mesa/drivers/dri/i965/gen8_misc_state.c82
8 files changed, 51 insertions, 97 deletions
diff --git a/src/mesa/drivers/dri/i965/Makefile.sources b/src/mesa/drivers/dri/i965/Makefile.sources
index 98c3e05412d..164e428710d 100644
--- a/src/mesa/drivers/dri/i965/Makefile.sources
+++ b/src/mesa/drivers/dri/i965/Makefile.sources
@@ -215,7 +215,6 @@ i965_FILES = \
gen8_ds_state.c \
gen8_gs_state.c \
gen8_hs_state.c \
- gen8_misc_state.c \
gen8_multisample_state.c \
gen8_ps_state.c \
gen8_sf_state.c \
diff --git a/src/mesa/drivers/dri/i965/brw_misc_state.c b/src/mesa/drivers/dri/i965/brw_misc_state.c
index 436a61902bb..c72f607785a 100644
--- a/src/mesa/drivers/dri/i965/brw_misc_state.c
+++ b/src/mesa/drivers/dri/i965/brw_misc_state.c
@@ -1063,8 +1063,8 @@ const struct brw_tracked_state brw_invariant_state = {
* surface state objects, but not the surfaces that the surface state
* objects point to.
*/
-static void
-upload_state_base_address(struct brw_context *brw)
+void
+brw_upload_state_base_address(struct brw_context *brw)
{
/* FINISHME: According to section 3.6.1 "STATE_BASE_ADDRESS" of
* vol1a of the G45 PRM, MI_FLUSH with the ISC invalidate should be
@@ -1075,7 +1075,45 @@ upload_state_base_address(struct brw_context *brw)
* maybe this isn't required for us in particular.
*/
- if (brw->gen >= 6) {
+ if (brw->gen >= 8) {
+ uint32_t mocs_wb = brw->gen >= 9 ? SKL_MOCS_WB : BDW_MOCS_WB;
+ int pkt_len = brw->gen >= 9 ? 19 : 16;
+
+ BEGIN_BATCH(pkt_len);
+ OUT_BATCH(CMD_STATE_BASE_ADDRESS << 16 | (pkt_len - 2));
+ /* General state base address: stateless DP read/write requests */
+ OUT_BATCH(mocs_wb << 4 | 1);
+ OUT_BATCH(0);
+ OUT_BATCH(mocs_wb << 16);
+ /* Surface state base address: */
+ OUT_RELOC64(brw->batch.bo, I915_GEM_DOMAIN_SAMPLER, 0,
+ mocs_wb << 4 | 1);
+ /* Dynamic state base address: */
+ OUT_RELOC64(brw->batch.bo,
+ I915_GEM_DOMAIN_RENDER | I915_GEM_DOMAIN_INSTRUCTION, 0,
+ mocs_wb << 4 | 1);
+ /* Indirect object base address: MEDIA_OBJECT data */
+ OUT_BATCH(mocs_wb << 4 | 1);
+ OUT_BATCH(0);
+ /* Instruction base address: shader kernels (incl. SIP) */
+ OUT_RELOC64(brw->cache.bo, I915_GEM_DOMAIN_INSTRUCTION, 0,
+ mocs_wb << 4 | 1);
+
+ /* General state buffer size */
+ OUT_BATCH(0xfffff001);
+ /* Dynamic state buffer size */
+ OUT_BATCH(ALIGN(brw->batch.bo->size, 4096) | 1);
+ /* Indirect object upper bound */
+ OUT_BATCH(0xfffff001);
+ /* Instruction access upper bound */
+ OUT_BATCH(ALIGN(brw->cache.bo->size, 4096) | 1);
+ if (brw->gen >= 9) {
+ OUT_BATCH(1);
+ OUT_BATCH(0);
+ OUT_BATCH(0);
+ }
+ ADVANCE_BATCH();
+ } else if (brw->gen >= 6) {
uint8_t mocs = brw->gen == 7 ? GEN7_MOCS_L3 : 0;
BEGIN_BATCH(10);
@@ -1171,5 +1209,5 @@ const struct brw_tracked_state brw_state_base_address = {
.brw = BRW_NEW_BATCH |
BRW_NEW_PROGRAM_CACHE,
},
- .emit = upload_state_base_address
+ .emit = brw_upload_state_base_address
};
diff --git a/src/mesa/drivers/dri/i965/brw_state.h b/src/mesa/drivers/dri/i965/brw_state.h
index 7adebad7f3b..880f44e553b 100644
--- a/src/mesa/drivers/dri/i965/brw_state.h
+++ b/src/mesa/drivers/dri/i965/brw_state.h
@@ -167,7 +167,6 @@ extern const struct brw_tracked_state gen8_wm_state;
extern const struct brw_tracked_state gen8_raster_state;
extern const struct brw_tracked_state gen8_sbe_state;
extern const struct brw_tracked_state gen8_sf_state;
-extern const struct brw_tracked_state gen8_state_base_address;
extern const struct brw_tracked_state gen8_sol_state;
extern const struct brw_tracked_state gen8_sf_clip_viewport;
extern const struct brw_tracked_state gen8_vertices;
@@ -194,13 +193,13 @@ void brw_upload_invariant_state(struct brw_context *brw);
uint32_t
brw_depthbuffer_format(struct brw_context *brw);
+void brw_upload_state_base_address(struct brw_context *brw);
+
+
/* gen8_depth_state.c */
void gen8_write_pma_stall_bits(struct brw_context *brw,
uint32_t pma_stall_bits);
-/* gen8_misc_state.c */
-void gen8_upload_state_base_address(struct brw_context *brw);
-
/***********************************************************************
* brw_state.c
*/
diff --git a/src/mesa/drivers/dri/i965/brw_state_upload.c b/src/mesa/drivers/dri/i965/brw_state_upload.c
index a70b246c5ce..ed92a85f923 100644
--- a/src/mesa/drivers/dri/i965/brw_state_upload.c
+++ b/src/mesa/drivers/dri/i965/brw_state_upload.c
@@ -284,7 +284,7 @@ static const struct brw_tracked_state *gen7_compute_atoms[] =
static const struct brw_tracked_state *gen8_render_atoms[] =
{
/* Command packets: */
- &gen8_state_base_address,
+ &brw_state_base_address,
&brw_cc_vp,
&gen8_sf_clip_viewport,
@@ -383,7 +383,7 @@ static const struct brw_tracked_state *gen8_render_atoms[] =
static const struct brw_tracked_state *gen8_compute_atoms[] =
{
- &gen8_state_base_address,
+ &brw_state_base_address,
&gen7_l3_state,
&brw_cs_image_surfaces,
&gen7_cs_push_constants,
diff --git a/src/mesa/drivers/dri/i965/gen6_blorp.c b/src/mesa/drivers/dri/i965/gen6_blorp.c
index b2a2d699549..9d72745d31e 100644
--- a/src/mesa/drivers/dri/i965/gen6_blorp.c
+++ b/src/mesa/drivers/dri/i965/gen6_blorp.c
@@ -997,7 +997,7 @@ gen6_blorp_exec(struct brw_context *brw,
brw_emit_post_sync_nonzero_flush(brw);
if (brw_state_base_address.dirty.brw & brw->ctx.NewDriverState)
- brw_state_base_address.emit(brw);
+ brw_upload_state_base_address(brw);
gen6_emit_3dstate_multisample(brw, params->dst.num_samples);
gen6_emit_3dstate_sample_mask(brw,
diff --git a/src/mesa/drivers/dri/i965/gen7_blorp.c b/src/mesa/drivers/dri/i965/gen7_blorp.c
index ea5f4c84479..494ed46dc70 100644
--- a/src/mesa/drivers/dri/i965/gen7_blorp.c
+++ b/src/mesa/drivers/dri/i965/gen7_blorp.c
@@ -818,7 +818,7 @@ gen7_blorp_exec(struct brw_context *brw,
uint32_t wm_bind_bo_offset = 0;
if (brw_state_base_address.dirty.brw & brw->ctx.NewDriverState)
- brw_state_base_address.emit(brw);
+ brw_upload_state_base_address(brw);
gen6_emit_3dstate_multisample(brw, params->dst.num_samples);
gen6_emit_3dstate_sample_mask(brw,
diff --git a/src/mesa/drivers/dri/i965/gen8_blorp.c b/src/mesa/drivers/dri/i965/gen8_blorp.c
index eefdc93d0df..6a783a75df9 100644
--- a/src/mesa/drivers/dri/i965/gen8_blorp.c
+++ b/src/mesa/drivers/dri/i965/gen8_blorp.c
@@ -653,8 +653,8 @@ gen8_blorp_exec(struct brw_context *brw, const struct brw_blorp_params *params)
{
uint32_t wm_bind_bo_offset = 0;
- if (gen8_state_base_address.dirty.brw & brw->ctx.NewDriverState)
- gen8_upload_state_base_address(brw);
+ if (brw_state_base_address.dirty.brw & brw->ctx.NewDriverState)
+ brw_upload_state_base_address(brw);
gen7_blorp_emit_cc_viewport(brw);
gen7_l3_state.emit(brw);
diff --git a/src/mesa/drivers/dri/i965/gen8_misc_state.c b/src/mesa/drivers/dri/i965/gen8_misc_state.c
deleted file mode 100644
index b20038eaacf..00000000000
--- a/src/mesa/drivers/dri/i965/gen8_misc_state.c
+++ /dev/null
@@ -1,82 +0,0 @@
-/*
- * Copyright © 2012 Intel Corporation
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice (including the next
- * paragraph) shall be included in all copies or substantial portions of the
- * Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
- * IN THE SOFTWARE.
- */
-
-#include "intel_batchbuffer.h"
-#include "brw_context.h"
-#include "brw_state.h"
-#include "brw_defines.h"
-
-/**
- * Define the base addresses which some state is referenced from.
- */
-void gen8_upload_state_base_address(struct brw_context *brw)
-{
- uint32_t mocs_wb = brw->gen >= 9 ? SKL_MOCS_WB : BDW_MOCS_WB;
- int pkt_len = brw->gen >= 9 ? 19 : 16;
-
- BEGIN_BATCH(pkt_len);
- OUT_BATCH(CMD_STATE_BASE_ADDRESS << 16 | (pkt_len - 2));
- /* General state base address: stateless DP read/write requests */
- OUT_BATCH(mocs_wb << 4 | 1);
- OUT_BATCH(0);
- OUT_BATCH(mocs_wb << 16);
- /* Surface state base address: */
- OUT_RELOC64(brw->batch.bo, I915_GEM_DOMAIN_SAMPLER, 0,
- mocs_wb << 4 | 1);
- /* Dynamic state base address: */
- OUT_RELOC64(brw->batch.bo,
- I915_GEM_DOMAIN_RENDER | I915_GEM_DOMAIN_INSTRUCTION, 0,
- mocs_wb << 4 | 1);
- /* Indirect object base address: MEDIA_OBJECT data */
- OUT_BATCH(mocs_wb << 4 | 1);
- OUT_BATCH(0);
- /* Instruction base address: shader kernels (incl. SIP) */
- OUT_RELOC64(brw->cache.bo, I915_GEM_DOMAIN_INSTRUCTION, 0,
- mocs_wb << 4 | 1);
-
- /* General state buffer size */
- OUT_BATCH(0xfffff001);
- /* Dynamic state buffer size */
- OUT_BATCH(ALIGN(brw->batch.bo->size, 4096) | 1);
- /* Indirect object upper bound */
- OUT_BATCH(0xfffff001);
- /* Instruction access upper bound */
- OUT_BATCH(ALIGN(brw->cache.bo->size, 4096) | 1);
- if (brw->gen >= 9) {
- OUT_BATCH(1);
- OUT_BATCH(0);
- OUT_BATCH(0);
- }
- ADVANCE_BATCH();
-
- brw->ctx.NewDriverState |= BRW_NEW_STATE_BASE_ADDRESS;
-}
-
-const struct brw_tracked_state gen8_state_base_address = {
- .dirty = {
- .mesa = 0,
- .brw = BRW_NEW_BATCH |
- BRW_NEW_PROGRAM_CACHE,
- },
- .emit = gen8_upload_state_base_address
-};
generated by cgit v1.2.3 (git 2.39.1) at 2024-12-04 17:33:36 +0000