diff options
Diffstat (limited to 'src')
28 files changed, 170 insertions, 170 deletions
diff --git a/src/mesa/drivers/dri/i965/brw_blorp.c b/src/mesa/drivers/dri/i965/brw_blorp.c index e1ea208c41c..23fe3aa3f9a 100644 --- a/src/mesa/drivers/dri/i965/brw_blorp.c +++ b/src/mesa/drivers/dri/i965/brw_blorp.c @@ -66,7 +66,7 @@ brw_blorp_init(struct brw_context *brw) { blorp_init(&brw->blorp, brw, &brw->isl_dev); - brw->blorp.compiler = brw->intelScreen->compiler; + brw->blorp.compiler = brw->screen->compiler; switch (brw->gen) { case 6: diff --git a/src/mesa/drivers/dri/i965/brw_clip.c b/src/mesa/drivers/dri/i965/brw_clip.c index 4c9d5c56c12..1d2070b6f8c 100644 --- a/src/mesa/drivers/dri/i965/brw_clip.c +++ b/src/mesa/drivers/dri/i965/brw_clip.c @@ -61,7 +61,7 @@ static void compile_clip_prog( struct brw_context *brw, /* Begin the compilation: */ - brw_init_codegen(brw->intelScreen->devinfo, &c.func, mem_ctx); + brw_init_codegen(brw->screen->devinfo, &c.func, mem_ctx); c.func.single_program_flow = 1; @@ -116,7 +116,7 @@ static void compile_clip_prog( struct brw_context *brw, if (unlikely(INTEL_DEBUG & DEBUG_CLIP)) { fprintf(stderr, "clip:\n"); - brw_disassemble(brw->intelScreen->devinfo, c.func.store, + brw_disassemble(brw->screen->devinfo, c.func.store, 0, program_size, stderr); fprintf(stderr, "\n"); } diff --git a/src/mesa/drivers/dri/i965/brw_context.c b/src/mesa/drivers/dri/i965/brw_context.c index 27e7d59c0a3..908eb6d1edc 100644 --- a/src/mesa/drivers/dri/i965/brw_context.c +++ b/src/mesa/drivers/dri/i965/brw_context.c @@ -80,9 +80,9 @@ const char *const brw_vendor_string = "Intel Open Source Technology Center"; static const char * -get_bsw_model(const struct intel_screen *intelScreen) +get_bsw_model(const struct intel_screen *screen) { - switch (intelScreen->eu_total) { + switch (screen->eu_total) { case 16: return "405"; case 12: @@ -93,13 +93,13 @@ get_bsw_model(const struct intel_screen *intelScreen) } const char * -brw_get_renderer_string(const struct intel_screen *intelScreen) +brw_get_renderer_string(const struct intel_screen *screen) { const char *chipset; static char buffer[128]; char *bsw = NULL; - switch (intelScreen->deviceID) { + switch (screen->deviceID) { #undef CHIPSET #define CHIPSET(id, symbol, str) case id: chipset = str; break; #include "pci_ids/i965_pci_ids.h" @@ -109,11 +109,11 @@ brw_get_renderer_string(const struct intel_screen *intelScreen) } /* Braswell branding is funny, so we have to fix it up here */ - if (intelScreen->deviceID == 0x22B1) { + if (screen->deviceID == 0x22B1) { bsw = strdup(chipset); char *needle = strstr(bsw, "XXX"); if (needle) { - memcpy(needle, get_bsw_model(intelScreen), 3); + memcpy(needle, get_bsw_model(screen), 3); chipset = bsw; } } @@ -134,7 +134,7 @@ intel_get_string(struct gl_context * ctx, GLenum name) case GL_RENDERER: return - (GLubyte *) brw_get_renderer_string(brw->intelScreen); + (GLubyte *) brw_get_renderer_string(brw->screen); default: return NULL; @@ -164,7 +164,7 @@ intel_update_framebuffer(struct gl_context *ctx, /* Quantize the derived default number of samples */ fb->DefaultGeometry._NumSamples = - intel_quantize_num_samples(brw->intelScreen, + intel_quantize_num_samples(brw->screen, fb->DefaultGeometry.NumSamples); } @@ -207,7 +207,7 @@ intel_texture_view_requires_resolve(struct brw_context *brw, const uint32_t brw_format = brw_format_for_mesa_format(intel_tex->_Format); - if (isl_format_supports_lossless_compression(brw->intelScreen->devinfo, + if (isl_format_supports_lossless_compression(brw->screen->devinfo, brw_format)) return false; @@ -366,7 +366,7 @@ intel_flush_front(struct gl_context *ctx) struct brw_context *brw = brw_context(ctx); __DRIcontext *driContext = brw->driContext; __DRIdrawable *driDrawable = driContext->driDrawablePriv; - __DRIscreen *const dri_screen = brw->intelScreen->driScrnPriv; + __DRIscreen *const dri_screen = brw->screen->driScrnPriv; if (brw->front_buffer_dirty && _mesa_is_winsys_fbo(ctx->DrawBuffer)) { if (flushFront(dri_screen) && driDrawable && @@ -463,7 +463,7 @@ brw_init_driver_functions(struct brw_context *brw, functions->NewTransformFeedback = brw_new_transform_feedback; functions->DeleteTransformFeedback = brw_delete_transform_feedback; - if (brw->intelScreen->has_mi_math_and_lrr) { + if (brw->screen->has_mi_math_and_lrr) { functions->BeginTransformFeedback = hsw_begin_transform_feedback; functions->EndTransformFeedback = hsw_end_transform_feedback; functions->PauseTransformFeedback = hsw_pause_transform_feedback; @@ -488,7 +488,7 @@ static void brw_initialize_context_constants(struct brw_context *brw) { struct gl_context *ctx = &brw->ctx; - const struct brw_compiler *compiler = brw->intelScreen->compiler; + const struct brw_compiler *compiler = brw->screen->compiler; const bool stage_exists[MESA_SHADER_STAGES] = { [MESA_SHADER_VERTEX] = true, @@ -591,10 +591,10 @@ brw_initialize_context_constants(struct brw_context *brw) BRW_MAX_SOL_BINDINGS / BRW_MAX_SOL_BUFFERS; ctx->Const.AlwaysUseGetTransformFeedbackVertexCount = - !brw->intelScreen->has_mi_math_and_lrr; + !brw->screen->has_mi_math_and_lrr; int max_samples; - const int *msaa_modes = intel_supported_msaa_modes(brw->intelScreen); + const int *msaa_modes = intel_supported_msaa_modes(brw->screen); const int clamp_max_samples = driQueryOptioni(&brw->optionCache, "clamp_max_samples"); @@ -768,7 +768,7 @@ brw_initialize_context_constants(struct brw_context *brw) /* We want the GLSL compiler to emit code that uses condition codes */ for (int i = 0; i < MESA_SHADER_STAGES; i++) { ctx->Const.ShaderCompilerOptions[i] = - brw->intelScreen->compiler->glsl_compiler_options[i]; + brw->screen->compiler->glsl_compiler_options[i]; } if (brw->gen >= 7) { @@ -805,7 +805,7 @@ static void brw_initialize_cs_context_constants(struct brw_context *brw) { struct gl_context *ctx = &brw->ctx; - const struct intel_screen *screen = brw->intelScreen; + const struct intel_screen *screen = brw->screen; const struct gen_device_info *devinfo = screen->devinfo; /* FINISHME: Do this for all platforms that the kernel supports */ @@ -852,7 +852,7 @@ brw_process_driconf_options(struct brw_context *brw) struct gl_context *ctx = &brw->ctx; driOptionCache *options = &brw->optionCache; - driParseConfigFiles(options, &brw->intelScreen->optionCache, + driParseConfigFiles(options, &brw->screen->optionCache, brw->driContext->driScreenPriv->myNum, "i965"); int bo_reuse_mode = driQueryOptioni(options, "bo_reuse"); @@ -889,7 +889,7 @@ brw_process_driconf_options(struct brw_context *brw) brw->precompile = driQueryOptionb(&brw->optionCache, "shader_precompile"); if (driQueryOptionb(&brw->optionCache, "precise_trig")) - brw->intelScreen->compiler->precise_trig = true; + brw->screen->compiler->precise_trig = true; ctx->Const.ForceGLSLExtensionsWarn = driQueryOptionb(options, "force_glsl_extensions_warn"); @@ -945,7 +945,7 @@ brwCreateContext(gl_api api, driContextPriv->driverPrivate = brw; brw->driContext = driContextPriv; - brw->intelScreen = screen; + brw->screen = screen; brw->bufmgr = screen->bufmgr; brw->gen = devinfo->gen; @@ -1442,7 +1442,7 @@ void intel_update_renderbuffers(__DRIcontext *context, __DRIdrawable *drawable) { struct brw_context *brw = context->driverPrivate; - __DRIscreen *dri_screen = brw->intelScreen->driScrnPriv; + __DRIscreen *dri_screen = brw->screen->driScrnPriv; /* Set this up front, so that in case our buffers get invalidated * while we're getting new buffers, we don't clobber the stamp and @@ -1516,7 +1516,7 @@ intel_query_dri2_buffers(struct brw_context *brw, __DRIbuffer **buffers, int *buffer_count) { - __DRIscreen *dri_screen = brw->intelScreen->driScrnPriv; + __DRIscreen *dri_screen = brw->screen->driScrnPriv; struct gl_framebuffer *fb = drawable->driverPrivate; int i = 0; unsigned attachments[8]; @@ -1713,7 +1713,7 @@ static void intel_update_image_buffers(struct brw_context *brw, __DRIdrawable *drawable) { struct gl_framebuffer *fb = drawable->driverPrivate; - __DRIscreen *dri_screen = brw->intelScreen->driScrnPriv; + __DRIscreen *dri_screen = brw->screen->driScrnPriv; struct intel_renderbuffer *front_rb; struct intel_renderbuffer *back_rb; struct __DRIimageList images; diff --git a/src/mesa/drivers/dri/i965/brw_context.h b/src/mesa/drivers/dri/i965/brw_context.h index 2c55b5edcfd..eb1df40cfe1 100644 --- a/src/mesa/drivers/dri/i965/brw_context.h +++ b/src/mesa/drivers/dri/i965/brw_context.h @@ -1344,7 +1344,7 @@ struct brw_context bool draw_aux_buffer_disabled[MAX_DRAW_BUFFERS]; __DRIcontext *driContext; - struct intel_screen *intelScreen; + struct intel_screen *screen; }; /*====================================================================== @@ -1361,7 +1361,7 @@ extern void intelInitClearFuncs(struct dd_function_table *functions); extern const char *const brw_vendor_string; extern const char * -brw_get_renderer_string(const struct intel_screen *intelScreen); +brw_get_renderer_string(const struct intel_screen *screen); enum { DRI_CONF_BO_REUSE_DISABLED, diff --git a/src/mesa/drivers/dri/i965/brw_cs.c b/src/mesa/drivers/dri/i965/brw_cs.c index 30ff190df4e..a73673fabbf 100644 --- a/src/mesa/drivers/dri/i965/brw_cs.c +++ b/src/mesa/drivers/dri/i965/brw_cs.c @@ -84,7 +84,7 @@ brw_codegen_cs_prog(struct brw_context *brw, prog_data.base.total_shared = prog->Comp.SharedSize; } - assign_cs_binding_table_offsets(brw->intelScreen->devinfo, prog, + assign_cs_binding_table_offsets(brw->screen->devinfo, prog, &cp->program.Base, &prog_data); /* Allocate the references to the uniforms that will end up in the @@ -124,7 +124,7 @@ brw_codegen_cs_prog(struct brw_context *brw, st_index = brw_get_shader_time_index(brw, prog, &cp->program.Base, ST_CS); char *error_str; - program = brw_compile_cs(brw->intelScreen->compiler, brw, mem_ctx, + program = brw_compile_cs(brw->screen->compiler, brw, mem_ctx, key, &prog_data, cp->program.Base.nir, st_index, &program_size, &error_str); if (program == NULL) { @@ -148,7 +148,7 @@ brw_codegen_cs_prog(struct brw_context *brw, } } - const unsigned subslices = MAX2(brw->intelScreen->subslice_total, 1); + const unsigned subslices = MAX2(brw->screen->subslice_total, 1); /* WaCSScratchSize:hsw * diff --git a/src/mesa/drivers/dri/i965/brw_ff_gs.c b/src/mesa/drivers/dri/i965/brw_ff_gs.c index 9065e08d970..7c878e9f66e 100644 --- a/src/mesa/drivers/dri/i965/brw_ff_gs.c +++ b/src/mesa/drivers/dri/i965/brw_ff_gs.c @@ -63,7 +63,7 @@ brw_codegen_ff_gs_prog(struct brw_context *brw, /* Begin the compilation: */ - brw_init_codegen(brw->intelScreen->devinfo, &c.func, mem_ctx); + brw_init_codegen(brw->screen->devinfo, &c.func, mem_ctx); c.func.single_program_flow = 1; @@ -135,7 +135,7 @@ brw_codegen_ff_gs_prog(struct brw_context *brw, if (unlikely(INTEL_DEBUG & DEBUG_GS)) { fprintf(stderr, "gs:\n"); - brw_disassemble(brw->intelScreen->devinfo, c.func.store, + brw_disassemble(brw->screen->devinfo, c.func.store, 0, program_size, stderr); fprintf(stderr, "\n"); } diff --git a/src/mesa/drivers/dri/i965/brw_gs.c b/src/mesa/drivers/dri/i965/brw_gs.c index 152013f647f..2b472c69511 100644 --- a/src/mesa/drivers/dri/i965/brw_gs.c +++ b/src/mesa/drivers/dri/i965/brw_gs.c @@ -97,7 +97,7 @@ brw_codegen_gs_prog(struct brw_context *brw, struct brw_geometry_program *gp, struct brw_gs_prog_key *key) { - struct brw_compiler *compiler = brw->intelScreen->compiler; + struct brw_compiler *compiler = brw->screen->compiler; struct brw_stage_state *stage_state = &brw->gs.base; struct brw_gs_prog_data prog_data; bool start_busy = false; @@ -105,7 +105,7 @@ brw_codegen_gs_prog(struct brw_context *brw, memset(&prog_data, 0, sizeof(prog_data)); - assign_gs_binding_table_offsets(brw->intelScreen->devinfo, prog, + assign_gs_binding_table_offsets(brw->screen->devinfo, prog, &gp->program.Base, &prog_data); /* Allocate the references to the uniforms that will end up in the @@ -139,7 +139,7 @@ brw_codegen_gs_prog(struct brw_context *brw, ((1 << gp->program.Base.CullDistanceArraySize) - 1) << gp->program.Base.ClipDistanceArraySize; - brw_compute_vue_map(brw->intelScreen->devinfo, + brw_compute_vue_map(brw->screen->devinfo, &prog_data.base.vue_map, outputs_written, prog->SeparateShader); @@ -159,7 +159,7 @@ brw_codegen_gs_prog(struct brw_context *brw, unsigned program_size; char *error_str; const unsigned *program = - brw_compile_gs(brw->intelScreen->compiler, brw, mem_ctx, key, + brw_compile_gs(brw->screen->compiler, brw, mem_ctx, key, &prog_data, gs->Program->nir, prog, st_index, &program_size, &error_str); if (program == NULL) { diff --git a/src/mesa/drivers/dri/i965/brw_link.cpp b/src/mesa/drivers/dri/i965/brw_link.cpp index 2b1fa61e117..f5dbfcfca4b 100644 --- a/src/mesa/drivers/dri/i965/brw_link.cpp +++ b/src/mesa/drivers/dri/i965/brw_link.cpp @@ -92,7 +92,7 @@ process_glsl_ir(gl_shader_stage stage, struct gl_linked_shader *shader) { struct gl_context *ctx = &brw->ctx; - const struct brw_compiler *compiler = brw->intelScreen->compiler; + const struct brw_compiler *compiler = brw->screen->compiler; const struct gl_shader_compiler_options *options = &ctx->Const.ShaderCompilerOptions[shader->Stage]; @@ -210,7 +210,7 @@ extern "C" GLboolean brw_link_shader(struct gl_context *ctx, struct gl_shader_program *shProg) { struct brw_context *brw = brw_context(ctx); - const struct brw_compiler *compiler = brw->intelScreen->compiler; + const struct brw_compiler *compiler = brw->screen->compiler; unsigned int stage; for (stage = 0; stage < ARRAY_SIZE(shProg->_LinkedShaders); stage++) { diff --git a/src/mesa/drivers/dri/i965/brw_program.c b/src/mesa/drivers/dri/i965/brw_program.c index b39b90fdc46..a41f36e766b 100644 --- a/src/mesa/drivers/dri/i965/brw_program.c +++ b/src/mesa/drivers/dri/i965/brw_program.c @@ -88,7 +88,7 @@ brw_create_nir(struct brw_context *brw, (void)progress; - nir = brw_preprocess_nir(brw->intelScreen->compiler, nir); + nir = brw_preprocess_nir(brw->screen->compiler, nir); if (stage == MESA_SHADER_FRAGMENT) { static const struct nir_lower_wpos_ytransform_options wpos_options = { @@ -133,7 +133,7 @@ static struct gl_program *brwNewProgram( struct gl_context *ctx, case GL_VERTEX_PROGRAM_ARB: { struct brw_vertex_program *prog = CALLOC_STRUCT(brw_vertex_program); if (prog) { - prog->id = get_new_program_id(brw->intelScreen); + prog->id = get_new_program_id(brw->screen); return _mesa_init_gl_program(&prog->program.Base, target, id); } @@ -144,7 +144,7 @@ static struct gl_program *brwNewProgram( struct gl_context *ctx, case GL_FRAGMENT_PROGRAM_ARB: { struct brw_fragment_program *prog = CALLOC_STRUCT(brw_fragment_program); if (prog) { - prog->id = get_new_program_id(brw->intelScreen); + prog->id = get_new_program_id(brw->screen); return _mesa_init_gl_program(&prog->program.Base, target, id); } @@ -155,7 +155,7 @@ static struct gl_program *brwNewProgram( struct gl_context *ctx, case GL_GEOMETRY_PROGRAM_NV: { struct brw_geometry_program *prog = CALLOC_STRUCT(brw_geometry_program); if (prog) { - prog->id = get_new_program_id(brw->intelScreen); + prog->id = get_new_program_id(brw->screen); return _mesa_init_gl_program(&prog->program.Base, target, id); } else { @@ -166,7 +166,7 @@ static struct gl_program *brwNewProgram( struct gl_context *ctx, case GL_TESS_CONTROL_PROGRAM_NV: { struct brw_tess_ctrl_program *prog = CALLOC_STRUCT(brw_tess_ctrl_program); if (prog) { - prog->id = get_new_program_id(brw->intelScreen); + prog->id = get_new_program_id(brw->screen); return _mesa_init_gl_program(&prog->program.Base, target, id); } else { @@ -177,7 +177,7 @@ static struct gl_program *brwNewProgram( struct gl_context *ctx, case GL_TESS_EVALUATION_PROGRAM_NV: { struct brw_tess_eval_program *prog = CALLOC_STRUCT(brw_tess_eval_program); if (prog) { - prog->id = get_new_program_id(brw->intelScreen); + prog->id = get_new_program_id(brw->screen); return _mesa_init_gl_program(&prog->program.Base, target, id); } else { @@ -188,7 +188,7 @@ static struct gl_program *brwNewProgram( struct gl_context *ctx, case GL_COMPUTE_PROGRAM_NV: { struct brw_compute_program *prog = CALLOC_STRUCT(brw_compute_program); if (prog) { - prog->id = get_new_program_id(brw->intelScreen); + prog->id = get_new_program_id(brw->screen); return _mesa_init_gl_program(&prog->program.Base, target, id); } else { @@ -214,7 +214,7 @@ brwProgramStringNotify(struct gl_context *ctx, struct gl_program *prog) { struct brw_context *brw = brw_context(ctx); - const struct brw_compiler *compiler = brw->intelScreen->compiler; + const struct brw_compiler *compiler = brw->screen->compiler; switch (target) { case GL_FRAGMENT_PROGRAM_ARB: { @@ -225,7 +225,7 @@ brwProgramStringNotify(struct gl_context *ctx, if (newFP == curFP) brw->ctx.NewDriverState |= BRW_NEW_FRAGMENT_PROGRAM; - newFP->id = get_new_program_id(brw->intelScreen); + newFP->id = get_new_program_id(brw->screen); brw_add_texrect_params(prog); @@ -245,7 +245,7 @@ brwProgramStringNotify(struct gl_context *ctx, if (newVP->program.IsPositionInvariant) { _mesa_insert_mvp_code(ctx, &newVP->program); } - newVP->id = get_new_program_id(brw->intelScreen); + newVP->id = get_new_program_id(brw->screen); /* Also tell tnl about it: */ diff --git a/src/mesa/drivers/dri/i965/brw_queryobj.c b/src/mesa/drivers/dri/i965/brw_queryobj.c index 6ba2296371a..dda17de7157 100644 --- a/src/mesa/drivers/dri/i965/brw_queryobj.c +++ b/src/mesa/drivers/dri/i965/brw_queryobj.c @@ -495,7 +495,7 @@ brw_get_timestamp(struct gl_context *ctx) struct brw_context *brw = brw_context(ctx); uint64_t result = 0; - switch (brw->intelScreen->hw_has_timestamp) { + switch (brw->screen->hw_has_timestamp) { case 3: /* New kernel, always full 36bit accuracy */ drm_intel_reg_read(brw->bufmgr, TIMESTAMP | 1, &result); break; diff --git a/src/mesa/drivers/dri/i965/brw_sf.c b/src/mesa/drivers/dri/i965/brw_sf.c index dff3461d7fe..dd5b4cce552 100644 --- a/src/mesa/drivers/dri/i965/brw_sf.c +++ b/src/mesa/drivers/dri/i965/brw_sf.c @@ -59,7 +59,7 @@ static void compile_sf_prog( struct brw_context *brw, mem_ctx = ralloc_context(NULL); /* Begin the compilation: */ - brw_init_codegen(brw->intelScreen->devinfo, &c.func, mem_ctx); + brw_init_codegen(brw->screen->devinfo, &c.func, mem_ctx); c.key = *key; c.vue_map = brw->vue_map_geom_out; @@ -118,7 +118,7 @@ static void compile_sf_prog( struct brw_context *brw, if (unlikely(INTEL_DEBUG & DEBUG_SF)) { fprintf(stderr, "sf:\n"); - brw_disassemble(brw->intelScreen->devinfo, + brw_disassemble(brw->screen->devinfo, c.func.store, 0, program_size, stderr); fprintf(stderr, "\n"); } diff --git a/src/mesa/drivers/dri/i965/brw_state_dump.c b/src/mesa/drivers/dri/i965/brw_state_dump.c index 6cd61c21fac..b1eba6d3428 100644 --- a/src/mesa/drivers/dri/i965/brw_state_dump.c +++ b/src/mesa/drivers/dri/i965/brw_state_dump.c @@ -765,7 +765,7 @@ dump_prog_cache(struct brw_context *brw) } fprintf(stderr, "%s:\n", name); - brw_disassemble(brw->intelScreen->devinfo, brw->cache.bo->virtual, + brw_disassemble(brw->screen->devinfo, brw->cache.bo->virtual, item->offset, item->size, stderr); } } diff --git a/src/mesa/drivers/dri/i965/brw_surface_formats.c b/src/mesa/drivers/dri/i965/brw_surface_formats.c index 40b2689e4e0..d99d38670d0 100644 --- a/src/mesa/drivers/dri/i965/brw_surface_formats.c +++ b/src/mesa/drivers/dri/i965/brw_surface_formats.c @@ -288,7 +288,7 @@ brw_format_for_mesa_format(mesa_format mesa_format) void brw_init_surface_formats(struct brw_context *brw) { - const struct gen_device_info *devinfo = brw->intelScreen->devinfo; + const struct gen_device_info *devinfo = brw->screen->devinfo; struct gl_context *ctx = &brw->ctx; int gen; mesa_format format; diff --git a/src/mesa/drivers/dri/i965/brw_tcs.c b/src/mesa/drivers/dri/i965/brw_tcs.c index 44629ad3465..61d64e6cdfd 100644 --- a/src/mesa/drivers/dri/i965/brw_tcs.c +++ b/src/mesa/drivers/dri/i965/brw_tcs.c @@ -169,7 +169,7 @@ brw_codegen_tcs_prog(struct brw_context *brw, struct brw_tcs_prog_key *key) { struct gl_context *ctx = &brw->ctx; - const struct brw_compiler *compiler = brw->intelScreen->compiler; + const struct brw_compiler *compiler = brw->screen->compiler; const struct gen_device_info *devinfo = compiler->devinfo; struct brw_stage_state *stage_state = &brw->tcs.base; nir_shader *nir; diff --git a/src/mesa/drivers/dri/i965/brw_tes.c b/src/mesa/drivers/dri/i965/brw_tes.c index c2f78226086..aeaff96e54d 100644 --- a/src/mesa/drivers/dri/i965/brw_tes.c +++ b/src/mesa/drivers/dri/i965/brw_tes.c @@ -82,8 +82,8 @@ brw_codegen_tes_prog(struct brw_context *brw, struct brw_tess_eval_program *tep, struct brw_tes_prog_key *key) { - const struct brw_compiler *compiler = brw->intelScreen->compiler; - const struct gen_device_info *devinfo = brw->intelScreen->devinfo; + const struct brw_compiler *compiler = brw->screen->compiler; + const struct gen_device_info *devinfo = brw->screen->devinfo; struct brw_stage_state *stage_state = &brw->tes.base; nir_shader *nir = tep->program.Base.nir; struct brw_tes_prog_data prog_data; diff --git a/src/mesa/drivers/dri/i965/brw_vs.c b/src/mesa/drivers/dri/i965/brw_vs.c index 30499e7b9f2..c637304ce78 100644 --- a/src/mesa/drivers/dri/i965/brw_vs.c +++ b/src/mesa/drivers/dri/i965/brw_vs.c @@ -90,7 +90,7 @@ brw_codegen_vs_prog(struct brw_context *brw, struct brw_vertex_program *vp, struct brw_vs_prog_key *key) { - const struct brw_compiler *compiler = brw->intelScreen->compiler; + const struct brw_compiler *compiler = brw->screen->compiler; GLuint program_size; const GLuint *program; struct brw_vs_prog_data prog_data; @@ -112,7 +112,7 @@ brw_codegen_vs_prog(struct brw_context *brw, mem_ctx = ralloc_context(NULL); brw_assign_common_binding_table_offsets(MESA_SHADER_VERTEX, - brw->intelScreen->devinfo, + brw->screen->devinfo, prog, &vp->program.Base, &prog_data.base.base, 0); @@ -160,7 +160,7 @@ brw_codegen_vs_prog(struct brw_context *brw, ((1 << vp->program.Base.CullDistanceArraySize) - 1) << vp->program.Base.ClipDistanceArraySize; - brw_compute_vue_map(brw->intelScreen->devinfo, + brw_compute_vue_map(brw->screen->devinfo, &prog_data.base.vue_map, outputs_written, prog ? prog->SeparateShader || prog->_LinkedShaders[MESA_SHADER_TESS_EVAL] diff --git a/src/mesa/drivers/dri/i965/brw_wm.c b/src/mesa/drivers/dri/i965/brw_wm.c index fb96f2f26db..23674f6b01f 100644 --- a/src/mesa/drivers/dri/i965/brw_wm.c +++ b/src/mesa/drivers/dri/i965/brw_wm.c @@ -97,7 +97,7 @@ brw_codegen_wm_prog(struct brw_context *brw, if (!prog) prog_data.base.use_alt_mode = true; - assign_fs_binding_table_offsets(brw->intelScreen->devinfo, prog, + assign_fs_binding_table_offsets(brw->screen->devinfo, prog, &fp->program.Base, key, &prog_data); /* Allocate the references to the uniforms that will end up in the @@ -142,7 +142,7 @@ brw_codegen_wm_prog(struct brw_context *brw, } char *error_str = NULL; - program = brw_compile_fs(brw->intelScreen->compiler, brw, mem_ctx, + program = brw_compile_fs(brw->screen->compiler, brw, mem_ctx, key, &prog_data, fp->program.Base.nir, &fp->program.Base, st_index8, st_index16, true, brw->use_rep_send, diff --git a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c index 3068c84ca18..ba6fa5266c3 100644 --- a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c +++ b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c @@ -94,7 +94,7 @@ brw_emit_surface_state(struct brw_context *brw, surf.dim = get_isl_surf_dim(target); const enum isl_dim_layout dim_layout = - get_isl_dim_layout(brw->intelScreen->devinfo, mt->tiling, target); + get_isl_dim_layout(brw->screen->devinfo, mt->tiling, target); if (surf.dim_layout != dim_layout) { /* The layout of the specified texture target is not compatible with the @@ -441,7 +441,7 @@ brw_texture_view_sane(const struct brw_context *brw, if (!intel_miptree_is_lossless_compressed(brw, mt)) return true; - if (isl_format_supports_lossless_compression(brw->intelScreen->devinfo, + if (isl_format_supports_lossless_compression(brw->screen->devinfo, format)) return true; @@ -1150,7 +1150,7 @@ update_renderbuffer_read_surfaces(struct brw_context *brw) if (irb) { const unsigned format = brw->render_target_format[ _mesa_get_render_format(ctx, intel_rb_format(irb))]; - assert(isl_format_supports_sampling(brw->intelScreen->devinfo, + assert(isl_format_supports_sampling(brw->screen->devinfo, format)); /* Override the target of the texture if the render buffer is a @@ -1577,7 +1577,7 @@ const struct brw_tracked_state brw_cs_image_surfaces = { static uint32_t get_image_format(struct brw_context *brw, mesa_format format, GLenum access) { - const struct gen_device_info *devinfo = brw->intelScreen->devinfo; + const struct gen_device_info *devinfo = brw->screen->devinfo; uint32_t hw_format = brw_format_for_mesa_format(format); if (access == GL_WRITE_ONLY) { return hw_format; diff --git a/src/mesa/drivers/dri/i965/gen7_cs_state.c b/src/mesa/drivers/dri/i965/gen7_cs_state.c index dded30f7a4a..1aa4b2f669f 100644 --- a/src/mesa/drivers/dri/i965/gen7_cs_state.c +++ b/src/mesa/drivers/dri/i965/gen7_cs_state.c @@ -46,7 +46,7 @@ brw_upload_cs_state(struct brw_context *brw) struct brw_stage_state *stage_state = &brw->cs.base; struct brw_cs_prog_data *cs_prog_data = brw->cs.prog_data; struct brw_stage_prog_data *prog_data = &cs_prog_data->base; - const struct gen_device_info *devinfo = brw->intelScreen->devinfo; + const struct gen_device_info *devinfo = brw->screen->devinfo; if (INTEL_DEBUG & DEBUG_SHADER_TIME) { brw_emit_buffer_surface_state( @@ -96,7 +96,7 @@ brw_upload_cs_state(struct brw_context *brw) const uint32_t vfe_num_urb_entries = brw->gen >= 8 ? 2 : 0; const uint32_t vfe_gpgpu_mode = brw->gen == 7 ? SET_FIELD(1, GEN7_MEDIA_VFE_STATE_GPGPU_MODE) : 0; - const uint32_t subslices = MAX2(brw->intelScreen->subslice_total, 1); + const uint32_t subslices = MAX2(brw->screen->subslice_total, 1); OUT_BATCH(SET_FIELD(brw->max_cs_threads * subslices - 1, MEDIA_VFE_STATE_MAX_THREADS) | SET_FIELD(vfe_num_urb_entries, MEDIA_VFE_STATE_URB_ENTRIES) | diff --git a/src/mesa/drivers/dri/i965/gen7_l3_state.c b/src/mesa/drivers/dri/i965/gen7_l3_state.c index 75a2983b63d..ec494dfcd72 100644 --- a/src/mesa/drivers/dri/i965/gen7_l3_state.c +++ b/src/mesa/drivers/dri/i965/gen7_l3_state.c @@ -58,7 +58,7 @@ get_pipeline_state_l3_weights(const struct brw_context *brw) needs_slm |= prog_data && prog_data->total_shared; } - return gen_get_default_l3_weights(brw->intelScreen->devinfo, + return gen_get_default_l3_weights(brw->screen->devinfo, needs_dc, needs_slm); } @@ -174,7 +174,7 @@ setup_l3_config(struct brw_context *brw, const struct gen_l3_config *cfg) ADVANCE_BATCH(); - if (brw->is_haswell && brw->intelScreen->cmd_parser_version >= 4) { + if (brw->is_haswell && brw->screen->cmd_parser_version >= 4) { /* Enable L3 atomics on HSW if we have a DC partition, otherwise keep * them disabled to avoid crashing the system hard. */ @@ -197,7 +197,7 @@ setup_l3_config(struct brw_context *brw, const struct gen_l3_config *cfg) static void update_urb_size(struct brw_context *brw, const struct gen_l3_config *cfg) { - const struct gen_device_info *devinfo = brw->intelScreen->devinfo; + const struct gen_device_info *devinfo = brw->screen->devinfo; const unsigned sz = gen_get_l3_config_urb_size(devinfo, cfg); if (brw->urb.size != sz) { @@ -230,7 +230,7 @@ emit_l3_state(struct brw_context *brw) if (dw > dw_threshold && brw->can_do_pipelined_register_writes) { const struct gen_l3_config *const cfg = - gen_get_l3_config(brw->intelScreen->devinfo, w); + gen_get_l3_config(brw->screen->devinfo, w); setup_l3_config(brw, cfg); update_urb_size(brw, cfg); @@ -292,7 +292,7 @@ const struct brw_tracked_state gen7_l3_state = { void gen7_restore_default_l3_config(struct brw_context *brw) { - const struct gen_device_info *devinfo = brw->intelScreen->devinfo; + const struct gen_device_info *devinfo = brw->screen->devinfo; const struct gen_l3_config *const cfg = gen_get_default_l3_config(devinfo); if (cfg != brw->l3.config && brw->can_do_pipelined_register_writes) { diff --git a/src/mesa/drivers/dri/i965/gen7_urb.c b/src/mesa/drivers/dri/i965/gen7_urb.c index da0a3783c21..707e0739ea3 100644 --- a/src/mesa/drivers/dri/i965/gen7_urb.c +++ b/src/mesa/drivers/dri/i965/gen7_urb.c @@ -202,7 +202,7 @@ void gen7_upload_urb(struct brw_context *brw, unsigned vs_size, bool gs_present, bool tess_present) { - const struct gen_device_info *devinfo = brw->intelScreen->devinfo; + const struct gen_device_info *devinfo = brw->screen->devinfo; const int push_size_kB = (brw->gen >= 8 || (brw->is_haswell && brw->gt == 3)) ? 32 : 16; diff --git a/src/mesa/drivers/dri/i965/intel_batchbuffer.c b/src/mesa/drivers/dri/i965/intel_batchbuffer.c index 93593d7c5b7..f136fae6cc3 100644 --- a/src/mesa/drivers/dri/i965/intel_batchbuffer.c +++ b/src/mesa/drivers/dri/i965/intel_batchbuffer.c @@ -139,7 +139,7 @@ do_batch_dump(struct brw_context *brw) struct intel_batchbuffer *batch = &brw->batch; int ret; - decode = drm_intel_decode_context_alloc(brw->intelScreen->deviceID); + decode = drm_intel_decode_context_alloc(brw->screen->deviceID); if (!decode) return; @@ -305,7 +305,7 @@ throttle(struct brw_context *brw) } if (brw->need_flush_throttle) { - __DRIscreen *dri_screen = brw->intelScreen->driScrnPriv; + __DRIscreen *dri_screen = brw->screen->driScrnPriv; drmCommandNone(dri_screen->fd, DRM_I915_GEM_THROTTLE); brw->need_flush_throttle = false; } @@ -336,7 +336,7 @@ do_flush_locked(struct brw_context *brw) } } - if (!brw->intelScreen->no_hw) { + if (!brw->screen->no_hw) { int flags; if (brw->gen >= 6 && batch->ring == BLT_RING) { diff --git a/src/mesa/drivers/dri/i965/intel_extensions.c b/src/mesa/drivers/dri/i965/intel_extensions.c index 2eb155415d9..93eb966e008 100644 --- a/src/mesa/drivers/dri/i965/intel_extensions.c +++ b/src/mesa/drivers/dri/i965/intel_extensions.c @@ -323,7 +323,7 @@ intelInitExtensions(struct gl_context *ctx) ctx->Extensions.OES_depth_texture_cube_map = true; ctx->Extensions.OES_sample_variables = true; - ctx->Extensions.ARB_timer_query = brw->intelScreen->hw_has_timestamp; + ctx->Extensions.ARB_timer_query = brw->screen->hw_has_timestamp; /* Only enable this in core profile because other parts of Mesa behave * slightly differently when the extension is enabled. @@ -364,14 +364,14 @@ intelInitExtensions(struct gl_context *ctx) ctx->Extensions.ARB_transform_feedback3 = true; ctx->Extensions.ARB_transform_feedback_instanced = true; - if ((brw->gen >= 8 || brw->intelScreen->cmd_parser_version >= 5) && + if ((brw->gen >= 8 || brw->screen->cmd_parser_version >= 5) && ctx->Const.MaxComputeWorkGroupSize[0] >= 1024) { ctx->Extensions.ARB_compute_shader = true; ctx->Extensions.ARB_ES3_1_compatibility = brw->gen >= 8 || brw->is_haswell; } - if (brw->intelScreen->cmd_parser_version >= 2) + if (brw->screen->cmd_parser_version >= 2) brw->predicate.supported = true; } } @@ -385,7 +385,7 @@ intelInitExtensions(struct gl_context *ctx) ctx->Extensions.ARB_robust_buffer_access_behavior = true; } - if (brw->intelScreen->has_mi_math_and_lrr) { + if (brw->screen->has_mi_math_and_lrr) { ctx->Extensions.ARB_query_buffer_object = true; } diff --git a/src/mesa/drivers/dri/i965/intel_fbo.c b/src/mesa/drivers/dri/i965/intel_fbo.c index 807e3e7901f..cb2ee8b3d25 100644 --- a/src/mesa/drivers/dri/i965/intel_fbo.c +++ b/src/mesa/drivers/dri/i965/intel_fbo.c @@ -282,7 +282,7 @@ intel_alloc_private_renderbuffer_storage(struct gl_context * ctx, struct gl_rend GLuint width, GLuint height) { struct brw_context *brw = brw_context(ctx); - struct intel_screen *screen = brw->intelScreen; + struct intel_screen *screen = brw->screen; struct intel_renderbuffer *irb = intel_renderbuffer(rb); assert(rb->Format != MESA_FORMAT_NONE); @@ -332,7 +332,7 @@ intel_image_target_renderbuffer_storage(struct gl_context *ctx, { struct brw_context *brw = brw_context(ctx); struct intel_renderbuffer *irb; - __DRIscreen *dri_screen = brw->intelScreen->driScrnPriv; + __DRIscreen *dri_screen = brw->screen->driScrnPriv; __DRIimage *image; image = dri_screen->dri2.image->lookupEGLImage(dri_screen, image_handle, diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c index 427657c8771..5e19d542f5d 100644 --- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c +++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c @@ -262,7 +262,7 @@ intel_miptree_supports_non_msrt_fast_clear(struct brw_context *brw, if (brw->gen >= 9) { mesa_format linear_format = _mesa_get_srgb_format_linear(mt->format); const uint32_t brw_format = brw_format_for_mesa_format(linear_format); - return isl_format_supports_lossless_compression(brw->intelScreen->devinfo, + return isl_format_supports_lossless_compression(brw->screen->devinfo, brw_format); } else return true; @@ -3063,7 +3063,7 @@ intel_miptree_get_isl_surf(struct brw_context *brw, struct isl_surf *surf) { surf->dim = get_isl_surf_dim(mt->target); - surf->dim_layout = get_isl_dim_layout(brw->intelScreen->devinfo, + surf->dim_layout = get_isl_dim_layout(brw->screen->devinfo, mt->tiling, mt->target); if (mt->num_samples > 1) { diff --git a/src/mesa/drivers/dri/i965/intel_screen.c b/src/mesa/drivers/dri/i965/intel_screen.c index c580b9700e1..5b21df6e7fa 100644 --- a/src/mesa/drivers/dri/i965/intel_screen.c +++ b/src/mesa/drivers/dri/i965/intel_screen.c @@ -403,7 +403,7 @@ intel_create_image_from_name(__DRIscreen *dri_screen, int width, int height, int format, int name, int pitch, void *loaderPrivate) { - struct intel_screen *intelScreen = dri_screen->driverPrivate; + struct intel_screen *screen = dri_screen->driverPrivate; __DRIimage *image; int cpp; @@ -419,7 +419,7 @@ intel_create_image_from_name(__DRIscreen *dri_screen, image->width = width; image->height = height; image->pitch = pitch * cpp; - image->bo = drm_intel_bo_gem_create_from_name(intelScreen->bufmgr, "image", + image->bo = drm_intel_bo_gem_create_from_name(screen->bufmgr, "image", name); if (!image->bo) { free(image); @@ -542,7 +542,7 @@ intel_create_image(__DRIscreen *dri_screen, void *loaderPrivate) { __DRIimage *image; - struct intel_screen *intelScreen = dri_screen->driverPrivate; + struct intel_screen *screen = dri_screen->driverPrivate; uint32_t tiling; int cpp; unsigned long pitch; @@ -562,7 +562,7 @@ intel_create_image(__DRIscreen *dri_screen, return NULL; cpp = _mesa_get_format_bytes(image->format); - image->bo = drm_intel_bo_alloc_tiled(intelScreen->bufmgr, "image", + image->bo = drm_intel_bo_alloc_tiled(screen->bufmgr, "image", width, height, cpp, &tiling, &pitch, 0); if (image->bo == NULL) { @@ -698,7 +698,7 @@ intel_create_image_from_fds(__DRIscreen *dri_screen, int *fds, int num_fds, int *strides, int *offsets, void *loaderPrivate) { - struct intel_screen *intelScreen = dri_screen->driverPrivate; + struct intel_screen *screen = dri_screen->driverPrivate; struct intel_image_format *f; __DRIimage *image; int i, index; @@ -740,7 +740,7 @@ intel_create_image_from_fds(__DRIscreen *dri_screen, size = end; } - image->bo = drm_intel_bo_gem_create_from_prime(intelScreen->bufmgr, + image->bo = drm_intel_bo_gem_create_from_prime(screen->bufmgr, fds[0], size); if (image->bo == NULL) { free(image); @@ -867,7 +867,7 @@ static int brw_query_renderer_integer(__DRIscreen *dri_screen, int param, unsigned int *value) { - const struct intel_screen *const intelScreen = + const struct intel_screen *const screen = (struct intel_screen *) dri_screen->driverPrivate; switch (param) { @@ -875,7 +875,7 @@ brw_query_renderer_integer(__DRIscreen *dri_screen, value[0] = 0x8086; return 0; case __DRI2_RENDERER_DEVICE_ID: - value[0] = intelScreen->deviceID; + value[0] = screen->deviceID; return 0; case __DRI2_RENDERER_ACCELERATED: value[0] = 1; @@ -922,7 +922,7 @@ static int brw_query_renderer_string(__DRIscreen *dri_screen, int param, const char **value) { - const struct intel_screen *intelScreen = + const struct intel_screen *screen = (struct intel_screen *) dri_screen->driverPrivate; switch (param) { @@ -930,7 +930,7 @@ brw_query_renderer_string(__DRIscreen *dri_screen, value[0] = brw_vendor_string; return 0; case __DRI2_RENDERER_DEVICE_ID: - value[0] = brw_get_renderer_string(intelScreen); + value[0] = brw_get_renderer_string(screen); return 0; default: break; @@ -950,7 +950,7 @@ static const __DRIrobustnessExtension dri2Robustness = { .base = { __DRI2_ROBUSTNESS, 1 } }; -static const __DRIextension *intelScreenExtensions[] = { +static const __DRIextension *screenExtensions[] = { &intelTexBufferExtension.base, &intelFenceExtension.base, &intelFlushExtension.base, @@ -1011,12 +1011,12 @@ intel_get_integer(struct intel_screen *screen, int param) static void intelDestroyScreen(__DRIscreen * sPriv) { - struct intel_screen *intelScreen = sPriv->driverPrivate; + struct intel_screen *screen = sPriv->driverPrivate; - dri_bufmgr_destroy(intelScreen->bufmgr); - driDestroyOptionInfo(&intelScreen->optionCache); + dri_bufmgr_destroy(screen->bufmgr); + driDestroyOptionInfo(&screen->optionCache); - ralloc_free(intelScreen); + ralloc_free(screen); sPriv->driverPrivate = NULL; } @@ -1134,21 +1134,21 @@ intelDestroyBuffer(__DRIdrawable * driDrawPriv) } static void -intel_detect_sseu(struct intel_screen *intelScreen) +intel_detect_sseu(struct intel_screen *screen) { - assert(intelScreen->devinfo->gen >= 8); + assert(screen->devinfo->gen >= 8); int ret; - intelScreen->subslice_total = -1; - intelScreen->eu_total = -1; + screen->subslice_total = -1; + screen->eu_total = -1; - ret = intel_get_param(intelScreen, I915_PARAM_SUBSLICE_TOTAL, - &intelScreen->subslice_total); + ret = intel_get_param(screen, I915_PARAM_SUBSLICE_TOTAL, + &screen->subslice_total); if (ret < 0 && ret != -EINVAL) goto err_out; - ret = intel_get_param(intelScreen, - I915_PARAM_EU_TOTAL, &intelScreen->eu_total); + ret = intel_get_param(screen, + I915_PARAM_EU_TOTAL, &screen->eu_total); if (ret < 0 && ret != -EINVAL) goto err_out; @@ -1156,35 +1156,35 @@ intel_detect_sseu(struct intel_screen *intelScreen) * and we have to use conservative numbers for GPGPU on many platforms, but * otherwise, things will just work. */ - if (intelScreen->subslice_total < 1 || intelScreen->eu_total < 1) + if (screen->subslice_total < 1 || screen->eu_total < 1) _mesa_warning(NULL, "Kernel 4.1 required to properly query GPU properties.\n"); return; err_out: - intelScreen->subslice_total = -1; - intelScreen->eu_total = -1; + screen->subslice_total = -1; + screen->eu_total = -1; _mesa_warning(NULL, "Failed to query GPU properties (%s).\n", strerror(-ret)); } static bool -intel_init_bufmgr(struct intel_screen *intelScreen) +intel_init_bufmgr(struct intel_screen *screen) { - __DRIscreen *dri_screen = intelScreen->driScrnPriv; + __DRIscreen *dri_screen = screen->driScrnPriv; - intelScreen->no_hw = getenv("INTEL_NO_HW") != NULL; + screen->no_hw = getenv("INTEL_NO_HW") != NULL; - intelScreen->bufmgr = intel_bufmgr_gem_init(dri_screen->fd, BATCH_SZ); - if (intelScreen->bufmgr == NULL) { + screen->bufmgr = intel_bufmgr_gem_init(dri_screen->fd, BATCH_SZ); + if (screen->bufmgr == NULL) { fprintf(stderr, "[%s:%u] Error initializing buffer manager.\n", __func__, __LINE__); return false; } - drm_intel_bufmgr_gem_enable_fenced_relocs(intelScreen->bufmgr); + drm_intel_bufmgr_gem_enable_fenced_relocs(screen->bufmgr); - if (!intel_get_boolean(intelScreen, I915_PARAM_HAS_RELAXED_DELTA)) { + if (!intel_get_boolean(screen, I915_PARAM_HAS_RELAXED_DELTA)) { fprintf(stderr, "[%s: %u] Kernel 2.6.39 required.\n", __func__, __LINE__); return false; } @@ -1540,7 +1540,7 @@ shader_perf_log_mesa(void *data, const char *fmt, ...) static const __DRIconfig **intelInitScreen2(__DRIscreen *dri_screen) { - struct intel_screen *intelScreen; + struct intel_screen *screen; if (dri_screen->image.loader) { } else if (dri_screen->dri2.loader->base.version <= 2 || @@ -1552,43 +1552,43 @@ __DRIconfig **intelInitScreen2(__DRIscreen *dri_screen) } /* Allocate the private area */ - intelScreen = rzalloc(NULL, struct intel_screen); - if (!intelScreen) { + screen = rzalloc(NULL, struct intel_screen); + if (!screen) { fprintf(stderr, "\nERROR! Allocating private area failed\n"); return false; } /* parse information in __driConfigOptions */ - driParseOptionInfo(&intelScreen->optionCache, brw_config_options.xml); + driParseOptionInfo(&screen->optionCache, brw_config_options.xml); - intelScreen->driScrnPriv = dri_screen; - dri_screen->driverPrivate = (void *) intelScreen; + screen->driScrnPriv = dri_screen; + dri_screen->driverPrivate = (void *) screen; - if (!intel_init_bufmgr(intelScreen)) + if (!intel_init_bufmgr(screen)) return false; - intelScreen->deviceID = drm_intel_bufmgr_gem_get_devid(intelScreen->bufmgr); - intelScreen->devinfo = gen_get_device_info(intelScreen->deviceID); - if (!intelScreen->devinfo) + screen->deviceID = drm_intel_bufmgr_gem_get_devid(screen->bufmgr); + screen->devinfo = gen_get_device_info(screen->deviceID); + if (!screen->devinfo) return false; brw_process_intel_debug_variable(); if (INTEL_DEBUG & DEBUG_BUFMGR) - dri_bufmgr_set_debug(intelScreen->bufmgr, true); + dri_bufmgr_set_debug(screen->bufmgr, true); - if ((INTEL_DEBUG & DEBUG_SHADER_TIME) && intelScreen->devinfo->gen < 7) { + if ((INTEL_DEBUG & DEBUG_SHADER_TIME) && screen->devinfo->gen < 7) { fprintf(stderr, "shader_time debugging requires gen7 (Ivybridge) or better.\n"); INTEL_DEBUG &= ~DEBUG_SHADER_TIME; } if (INTEL_DEBUG & DEBUG_AUB) - drm_intel_bufmgr_gem_set_aub_dump(intelScreen->bufmgr, true); + drm_intel_bufmgr_gem_set_aub_dump(screen->bufmgr, true); #ifndef I915_PARAM_MMAP_GTT_VERSION #define I915_PARAM_MMAP_GTT_VERSION 40 /* XXX delete me with new libdrm */ #endif - if (intel_get_integer(intelScreen, I915_PARAM_MMAP_GTT_VERSION) >= 1) { + if (intel_get_integer(screen, I915_PARAM_MMAP_GTT_VERSION) >= 1) { /* Theorectically unlimited! At least for individual objects... * * Currently the entire (global) address space for all GTT maps is @@ -1604,7 +1604,7 @@ __DRIconfig **intelInitScreen2(__DRIscreen *dri_screen) * objects of the current maximum allocable size before running out * of mmap space. */ - intelScreen->max_gtt_map_object_size = UINT64_MAX; + screen->max_gtt_map_object_size = UINT64_MAX; } else { /* Estimate the size of the mappable aperture into the GTT. There's an * ioctl to get the whole GTT size, but not one to get the mappable subset. @@ -1619,30 +1619,30 @@ __DRIconfig **intelInitScreen2(__DRIscreen *dri_screen) * taken up by things like the framebuffer and the ringbuffer and such, so * be more conservative. */ - intelScreen->max_gtt_map_object_size = gtt_size / 4; + screen->max_gtt_map_object_size = gtt_size / 4; } - intelScreen->hw_has_swizzling = intel_detect_swizzling(intelScreen); - intelScreen->hw_has_timestamp = intel_detect_timestamp(intelScreen); + screen->hw_has_swizzling = intel_detect_swizzling(screen); + screen->hw_has_timestamp = intel_detect_timestamp(screen); /* GENs prior to 8 do not support EU/Subslice info */ - if (intelScreen->devinfo->gen >= 8) { - intel_detect_sseu(intelScreen); - } else if (intelScreen->devinfo->gen == 7) { - intelScreen->subslice_total = 1 << (intelScreen->devinfo->gt - 1); + if (screen->devinfo->gen >= 8) { + intel_detect_sseu(screen); + } else if (screen->devinfo->gen == 7) { + screen->subslice_total = 1 << (screen->devinfo->gt - 1); } const char *force_msaa = getenv("INTEL_FORCE_MSAA"); if (force_msaa) { - intelScreen->winsys_msaa_samples_override = - intel_quantize_num_samples(intelScreen, atoi(force_msaa)); + screen->winsys_msaa_samples_override = + intel_quantize_num_samples(screen, atoi(force_msaa)); printf("Forcing winsys sample count to %d\n", - intelScreen->winsys_msaa_samples_override); + screen->winsys_msaa_samples_override); } else { - intelScreen->winsys_msaa_samples_override = -1; + screen->winsys_msaa_samples_override = -1; } - set_max_gl_versions(intelScreen); + set_max_gl_versions(screen); /* Notification of GPU resets requires hardware contexts and a kernel new * enough to support DRM_IOCTL_I915_GET_RESET_STATS. If the ioctl is @@ -1653,41 +1653,41 @@ __DRIconfig **intelInitScreen2(__DRIscreen *dri_screen) * * Don't even try on pre-Gen6, since we don't attempt to use contexts there. */ - if (intelScreen->devinfo->gen >= 6) { + if (screen->devinfo->gen >= 6) { struct drm_i915_reset_stats stats; memset(&stats, 0, sizeof(stats)); const int ret = drmIoctl(dri_screen->fd, DRM_IOCTL_I915_GET_RESET_STATS, &stats); - intelScreen->has_context_reset_notification = + screen->has_context_reset_notification = (ret != -1 || errno != EINVAL); } - if (intel_get_param(intelScreen, I915_PARAM_CMD_PARSER_VERSION, - &intelScreen->cmd_parser_version) < 0) { - intelScreen->cmd_parser_version = 0; + if (intel_get_param(screen, I915_PARAM_CMD_PARSER_VERSION, + &screen->cmd_parser_version) < 0) { + screen->cmd_parser_version = 0; } /* Haswell requires command parser version 6 in order to write to the * MI_MATH GPR registers, and version 7 in order to use * MI_LOAD_REGISTER_REG (which all users of MI_MATH use). */ - intelScreen->has_mi_math_and_lrr = intelScreen->devinfo->gen >= 8 || - (intelScreen->devinfo->is_haswell && - intelScreen->cmd_parser_version >= 7); - - dri_screen->extensions = !intelScreen->has_context_reset_notification - ? intelScreenExtensions : intelRobustScreenExtensions; - - intelScreen->compiler = brw_compiler_create(intelScreen, - intelScreen->devinfo); - intelScreen->compiler->shader_debug_log = shader_debug_log_mesa; - intelScreen->compiler->shader_perf_log = shader_perf_log_mesa; - intelScreen->program_id = 1; - - if (intelScreen->devinfo->has_resource_streamer) { - intelScreen->has_resource_streamer = - intel_get_boolean(intelScreen, I915_PARAM_HAS_RESOURCE_STREAMER); + screen->has_mi_math_and_lrr = screen->devinfo->gen >= 8 || + (screen->devinfo->is_haswell && + screen->cmd_parser_version >= 7); + + dri_screen->extensions = !screen->has_context_reset_notification + ? screenExtensions : intelRobustScreenExtensions; + + screen->compiler = brw_compiler_create(screen, + screen->devinfo); + screen->compiler->shader_debug_log = shader_debug_log_mesa; + screen->compiler->shader_perf_log = shader_perf_log_mesa; + screen->program_id = 1; + + if (screen->devinfo->has_resource_streamer) { + screen->has_resource_streamer = + intel_get_boolean(screen, I915_PARAM_HAS_RESOURCE_STREAMER); } return (const __DRIconfig**) intel_screen_make_configs(dri_screen); @@ -1704,7 +1704,7 @@ intelAllocateBuffer(__DRIscreen *dri_screen, int width, int height) { struct intel_buffer *intelBuffer; - struct intel_screen *intelScreen = dri_screen->driverPrivate; + struct intel_screen *screen = dri_screen->driverPrivate; assert(attachment == __DRI_BUFFER_FRONT_LEFT || attachment == __DRI_BUFFER_BACK_LEFT); @@ -1717,7 +1717,7 @@ intelAllocateBuffer(__DRIscreen *dri_screen, uint32_t tiling = I915_TILING_X; unsigned long pitch; int cpp = format / 8; - intelBuffer->bo = drm_intel_bo_alloc_tiled(intelScreen->bufmgr, + intelBuffer->bo = drm_intel_bo_alloc_tiled(screen->bufmgr, "intelAllocateBuffer", width, height, diff --git a/src/mesa/drivers/dri/i965/intel_tex.c b/src/mesa/drivers/dri/i965/intel_tex.c index 09e8a7d6cc5..12a346838f3 100644 --- a/src/mesa/drivers/dri/i965/intel_tex.c +++ b/src/mesa/drivers/dri/i965/intel_tex.c @@ -71,7 +71,7 @@ intel_alloc_texture_image_buffer(struct gl_context *ctx, /* Quantize sample count */ if (image->NumSamples) { - image->NumSamples = intel_quantize_num_samples(brw->intelScreen, image->NumSamples); + image->NumSamples = intel_quantize_num_samples(brw->screen, image->NumSamples); if (!image->NumSamples) return false; } @@ -128,7 +128,7 @@ intel_alloc_texture_storage(struct gl_context *ctx, struct brw_context *brw = brw_context(ctx); struct intel_texture_object *intel_texobj = intel_texture_object(texobj); struct gl_texture_image *first_image = texobj->Image[0][0]; - int num_samples = intel_quantize_num_samples(brw->intelScreen, + int num_samples = intel_quantize_num_samples(brw->screen, first_image->NumSamples); const int numFaces = _mesa_num_tex_faces(texobj->Target); int face; diff --git a/src/mesa/drivers/dri/i965/intel_tex_image.c b/src/mesa/drivers/dri/i965/intel_tex_image.c index a7c321bb6b6..4454e53916a 100644 --- a/src/mesa/drivers/dri/i965/intel_tex_image.c +++ b/src/mesa/drivers/dri/i965/intel_tex_image.c @@ -384,7 +384,7 @@ intel_image_target_texture_2d(struct gl_context *ctx, GLenum target, { struct brw_context *brw = brw_context(ctx); struct intel_mipmap_tree *mt; - __DRIscreen *dri_screen = brw->intelScreen->driScrnPriv; + __DRIscreen *dri_screen = brw->screen->driScrnPriv; __DRIimage *image; image = dri_screen->dri2.image->lookupEGLImage(dri_screen, image_handle, |