diff options
Diffstat (limited to 'src')
29 files changed, 61 insertions, 64 deletions
diff --git a/src/mesa/drivers/dri/i965/brw_clip_state.c b/src/mesa/drivers/dri/i965/brw_clip_state.c index d1c2938eee0..e0cc6499dd3 100644 --- a/src/mesa/drivers/dri/i965/brw_clip_state.c +++ b/src/mesa/drivers/dri/i965/brw_clip_state.c @@ -146,7 +146,7 @@ brw_upload_clip_unit(struct brw_context *brw) clip->clip5.api_mode = BRW_CLIP_API_OGL; clip->clip5.clip_mode = brw->clip.prog_data->clip_mode; - if (intel->is_g4x) + if (brw->is_g4x) clip->clip5.negative_w_clip_test = 1; clip->viewport_xmin = -1; diff --git a/src/mesa/drivers/dri/i965/brw_context.c b/src/mesa/drivers/dri/i965/brw_context.c index c05e3d56483..90198bc3cdd 100644 --- a/src/mesa/drivers/dri/i965/brw_context.c +++ b/src/mesa/drivers/dri/i965/brw_context.c @@ -341,7 +341,7 @@ brwCreateContext(int api, ctx->DriverFlags.NewRasterizerDiscard = BRW_NEW_RASTERIZER_DISCARD; ctx->DriverFlags.NewUniformBuffer = BRW_NEW_UNIFORM_BUFFER; - if (intel->is_g4x || intel->gen >= 5) { + if (brw->is_g4x || intel->gen >= 5) { brw->CMD_VF_STATISTICS = GM45_3DSTATE_VF_STATISTICS; brw->CMD_PIPELINE_SELECT = CMD_PIPELINE_SELECT_GM45; brw->has_surface_tile_offset = true; @@ -357,7 +357,7 @@ brwCreateContext(int api, /* WM maximum threads is number of EUs times number of threads per EU. */ assert(intel->gen <= 7); - if (intel->is_haswell) { + if (brw->is_haswell) { if (intel->gt == 1) { brw->max_wm_threads = 102; brw->max_vs_threads = 70; @@ -417,7 +417,7 @@ brwCreateContext(int api, brw->max_vs_threads = 72; brw->max_gs_threads = 32; brw->max_wm_threads = 12 * 6; - } else if (intel->is_g4x) { + } else if (brw->is_g4x) { brw->urb.size = 384; brw->max_vs_threads = 32; brw->max_gs_threads = 2; diff --git a/src/mesa/drivers/dri/i965/brw_context.h b/src/mesa/drivers/dri/i965/brw_context.h index 7075a610659..c6e75d562a5 100644 --- a/src/mesa/drivers/dri/i965/brw_context.h +++ b/src/mesa/drivers/dri/i965/brw_context.h @@ -876,6 +876,11 @@ struct brw_context uint32_t max_gtt_map_object_size; bool emit_state_always; + + bool is_g4x; + bool is_baytrail; + bool is_haswell; + bool has_hiz; bool has_separate_stencil; bool must_use_separate_stencil; diff --git a/src/mesa/drivers/dri/i965/brw_draw_upload.c b/src/mesa/drivers/dri/i965/brw_draw_upload.c index 3e8fcb1e12b..55b07b56f45 100644 --- a/src/mesa/drivers/dri/i965/brw_draw_upload.c +++ b/src/mesa/drivers/dri/i965/brw_draw_upload.c @@ -265,7 +265,7 @@ get_surface_type(struct brw_context *brw, return ubyte_types_norm[size]; } case GL_FIXED: - if (intel->gen >= 8 || intel->is_haswell) + if (intel->gen >= 8 || brw->is_haswell) return fixed_point_types[size]; /* This produces GL_FIXED inputs as values between INT32_MIN and @@ -279,7 +279,7 @@ get_surface_type(struct brw_context *brw, */ case GL_INT_2_10_10_10_REV: assert(size == 4); - if (intel->gen >= 8 || intel->is_haswell) { + if (intel->gen >= 8 || brw->is_haswell) { return glarray->Format == GL_BGRA ? BRW_SURFACEFORMAT_B10G10R10A2_SNORM : BRW_SURFACEFORMAT_R10G10B10A2_SNORM; @@ -287,7 +287,7 @@ get_surface_type(struct brw_context *brw, return BRW_SURFACEFORMAT_R10G10B10A2_UINT; case GL_UNSIGNED_INT_2_10_10_10_REV: assert(size == 4); - if (intel->gen >= 8 || intel->is_haswell) { + if (intel->gen >= 8 || brw->is_haswell) { return glarray->Format == GL_BGRA ? BRW_SURFACEFORMAT_B10G10R10A2_UNORM : BRW_SURFACEFORMAT_R10G10B10A2_UNORM; @@ -304,7 +304,7 @@ get_surface_type(struct brw_context *brw, */ if (glarray->Type == GL_INT_2_10_10_10_REV) { assert(size == 4); - if (intel->gen >= 8 || intel->is_haswell) { + if (intel->gen >= 8 || brw->is_haswell) { return glarray->Format == GL_BGRA ? BRW_SURFACEFORMAT_B10G10R10A2_SSCALED : BRW_SURFACEFORMAT_R10G10B10A2_SSCALED; @@ -312,7 +312,7 @@ get_surface_type(struct brw_context *brw, return BRW_SURFACEFORMAT_R10G10B10A2_UINT; } else if (glarray->Type == GL_UNSIGNED_INT_2_10_10_10_REV) { assert(size == 4); - if (intel->gen >= 8 || intel->is_haswell) { + if (intel->gen >= 8 || brw->is_haswell) { return glarray->Format == GL_BGRA ? BRW_SURFACEFORMAT_B10G10R10A2_USCALED : BRW_SURFACEFORMAT_R10G10B10A2_USCALED; @@ -331,7 +331,7 @@ get_surface_type(struct brw_context *brw, case GL_UNSIGNED_SHORT: return ushort_types_scale[size]; case GL_UNSIGNED_BYTE: return ubyte_types_scale[size]; case GL_FIXED: - if (intel->gen >= 8 || intel->is_haswell) + if (intel->gen >= 8 || brw->is_haswell) return fixed_point_types[size]; /* This produces GL_FIXED inputs as values between INT32_MIN and @@ -886,14 +886,13 @@ const struct brw_tracked_state brw_indices = { static void brw_emit_index_buffer(struct brw_context *brw) { - struct intel_context *intel = &brw->intel; const struct _mesa_index_buffer *index_buffer = brw->ib.ib; GLuint cut_index_setting; if (index_buffer == NULL) return; - if (brw->prim_restart.enable_cut_index && !intel->is_haswell) { + if (brw->prim_restart.enable_cut_index && !brw->is_haswell) { cut_index_setting = BRW_CUT_INDEX_ENABLE; } else { cut_index_setting = 0; diff --git a/src/mesa/drivers/dri/i965/brw_eu_emit.c b/src/mesa/drivers/dri/i965/brw_eu_emit.c index f2cacd17762..41feaa99eb8 100644 --- a/src/mesa/drivers/dri/i965/brw_eu_emit.c +++ b/src/mesa/drivers/dri/i965/brw_eu_emit.c @@ -660,7 +660,7 @@ brw_set_dp_read_message(struct brw_compile *p, insn->bits3.dp_read_gen5.msg_control = msg_control; insn->bits3.dp_read_gen5.msg_type = msg_type; insn->bits3.dp_read_gen5.target_cache = target_cache; - } else if (intel->is_g4x) { + } else if (brw->is_g4x) { insn->bits3.dp_read_g4x.binding_table_index = binding_table_index; /*0:7*/ insn->bits3.dp_read_g4x.msg_control = msg_control; /*8:10*/ insn->bits3.dp_read_g4x.msg_type = msg_type; /*11:13*/ @@ -701,7 +701,7 @@ brw_set_sampler_message(struct brw_compile *p, insn->bits3.sampler_gen5.sampler = sampler; insn->bits3.sampler_gen5.msg_type = msg_type; insn->bits3.sampler_gen5.simd_mode = simd_mode; - } else if (intel->is_g4x) { + } else if (brw->is_g4x) { insn->bits3.sampler_g4x.binding_table_index = binding_table_index; insn->bits3.sampler_g4x.sampler = sampler; insn->bits3.sampler_g4x.msg_type = msg_type; @@ -2498,6 +2498,7 @@ void brw_shader_time_add(struct brw_compile *p, struct brw_reg payload, uint32_t surf_index) { + struct brw_context *brw = p->brw; struct intel_context *intel = &p->brw->intel; assert(intel->gen >= 7); @@ -2516,7 +2517,7 @@ void brw_shader_time_add(struct brw_compile *p, payload.nr, 0)); uint32_t sfid, msg_type; - if (intel->is_haswell) { + if (brw->is_haswell) { sfid = HSW_SFID_DATAPORT_DATA_CACHE_1; msg_type = HSW_DATAPORT_DC_PORT1_UNTYPED_ATOMIC_OP; } else { diff --git a/src/mesa/drivers/dri/i965/brw_fs.cpp b/src/mesa/drivers/dri/i965/brw_fs.cpp index 65cb8ab8a9e..63e4b5a7ec8 100644 --- a/src/mesa/drivers/dri/i965/brw_fs.cpp +++ b/src/mesa/drivers/dri/i965/brw_fs.cpp @@ -2599,7 +2599,7 @@ fs_visitor::insert_gen4_post_send_dependency_workarounds(fs_inst *inst) void fs_visitor::insert_gen4_send_dependency_workarounds() { - if (intel->gen != 4 || intel->is_g4x) + if (intel->gen != 4 || brw->is_g4x) return; /* Note that we're done with register allocation, so GRF fs_regs always diff --git a/src/mesa/drivers/dri/i965/brw_fs_emit.cpp b/src/mesa/drivers/dri/i965/brw_fs_emit.cpp index c158016ba5e..5fe231df2b4 100644 --- a/src/mesa/drivers/dri/i965/brw_fs_emit.cpp +++ b/src/mesa/drivers/dri/i965/brw_fs_emit.cpp @@ -403,7 +403,7 @@ fs_generator::generate_tex(fs_inst *inst, struct brw_reg dst, struct brw_reg src case SHADER_OPCODE_TXD: if (inst->shadow_compare) { /* Gen7.5+. Otherwise, lowered by brw_lower_texture_gradients(). */ - assert(intel->is_haswell); + assert(brw->is_haswell); msg_type = HSW_SAMPLER_MESSAGE_SAMPLE_DERIV_COMPARE; } else { msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_DERIVS; @@ -1327,7 +1327,7 @@ fs_generator::generate_code(exec_list *instructions) generate_math1_gen7(inst, dst, src[0]); } else if (intel->gen == 6) { generate_math1_gen6(inst, dst, src[0]); - } else if (intel->gen == 5 || intel->is_g4x) { + } else if (intel->gen == 5 || brw->is_g4x) { generate_math_g45(inst, dst, src[0]); } else { generate_math_gen4(inst, dst, src[0]); diff --git a/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp b/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp index 3353f55479f..3ba4ec84bbf 100644 --- a/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp +++ b/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp @@ -970,7 +970,7 @@ fs_visitor::emit_texture_gen4(ir_texture *ir, fs_reg dst, fs_reg coordinate, */ orig_dst = dst; dst = fs_reg(GRF, virtual_grf_alloc(8), - (intel->is_g4x ? + (brw->is_g4x ? brw_type_for_base_type(ir->type) : BRW_REGISTER_TYPE_F)); } diff --git a/src/mesa/drivers/dri/i965/brw_lower_texture_gradients.cpp b/src/mesa/drivers/dri/i965/brw_lower_texture_gradients.cpp index 543c720aae5..e4e10b0d76a 100644 --- a/src/mesa/drivers/dri/i965/brw_lower_texture_gradients.cpp +++ b/src/mesa/drivers/dri/i965/brw_lower_texture_gradients.cpp @@ -169,7 +169,7 @@ brw_lower_texture_gradients(struct brw_context *brw, struct exec_list *instructions) { struct intel_context *intel = &brw->intel; - bool has_sample_d_c = intel->gen >= 8 || intel->is_haswell; + bool has_sample_d_c = intel->gen >= 8 || brw->is_haswell; lower_texture_grad_visitor v(has_sample_d_c); visit_list_elements(&v, instructions); diff --git a/src/mesa/drivers/dri/i965/brw_misc_state.c b/src/mesa/drivers/dri/i965/brw_misc_state.c index 141a0dfe124..37175204f03 100644 --- a/src/mesa/drivers/dri/i965/brw_misc_state.c +++ b/src/mesa/drivers/dri/i965/brw_misc_state.c @@ -385,7 +385,7 @@ brw_workaround_depthstencil_alignment(struct brw_context *brw, rebase_depth = true; /* We didn't even have intra-tile offsets before g45. */ - if (intel->gen == 4 && !intel->is_g4x) { + if (intel->gen == 4 && !brw->is_g4x) { if (tile_x || tile_y) rebase_depth = true; } @@ -444,7 +444,7 @@ brw_workaround_depthstencil_alignment(struct brw_context *brw, if (stencil_tile_x & 7 || stencil_tile_y & 7) rebase_stencil = true; - if (intel->gen == 4 && !intel->is_g4x) { + if (intel->gen == 4 && !brw->is_g4x) { if (stencil_tile_x || stencil_tile_y) rebase_stencil = true; } @@ -677,7 +677,7 @@ brw_emit_depth_stencil_hiz(struct brw_context *brw, unsigned int len; if (intel->gen >= 6) len = 7; - else if (intel->is_g4x || intel->gen == 5) + else if (brw->is_g4x || intel->gen == 5) len = 6; else len = 5; @@ -705,7 +705,7 @@ brw_emit_depth_stencil_hiz(struct brw_context *brw, ((height + tile_y - 1) << 19)); OUT_BATCH(0); - if (intel->is_g4x || intel->gen >= 5) + if (brw->is_g4x || intel->gen >= 5) OUT_BATCH(tile_x | (tile_y << 16)); else assert(tile_x == 0 && tile_y == 0); diff --git a/src/mesa/drivers/dri/i965/brw_primitive_restart.c b/src/mesa/drivers/dri/i965/brw_primitive_restart.c index 5fbc9333dfd..a98556b6328 100644 --- a/src/mesa/drivers/dri/i965/brw_primitive_restart.c +++ b/src/mesa/drivers/dri/i965/brw_primitive_restart.c @@ -79,10 +79,11 @@ can_cut_index_handle_prims(struct gl_context *ctx, GLuint nr_prims, const struct _mesa_index_buffer *ib) { + struct brw_context *brw = brw_context(ctx); struct intel_context *intel = intel_context(ctx); /* Otherwise Haswell can do it all. */ - if (intel->gen >= 8 || intel->is_haswell) + if (intel->gen >= 8 || brw->is_haswell) return true; if (!can_cut_index_handle_restart_index(ctx, ib)) { @@ -187,7 +188,7 @@ haswell_upload_cut_index(struct brw_context *brw) struct gl_context *ctx = &intel->ctx; /* Don't trigger on Ivybridge */ - if (!intel->is_haswell) + if (!brw->is_haswell) return; const unsigned cut_index_setting = diff --git a/src/mesa/drivers/dri/i965/brw_schedule_instructions.cpp b/src/mesa/drivers/dri/i965/brw_schedule_instructions.cpp index f95305acb87..66593586d8b 100644 --- a/src/mesa/drivers/dri/i965/brw_schedule_instructions.cpp +++ b/src/mesa/drivers/dri/i965/brw_schedule_instructions.cpp @@ -75,7 +75,7 @@ public: * closer to Gen7 than Gen4. */ if (intel->gen >= 6) - set_latency_gen7(intel->is_haswell); + set_latency_gen7(brw->is_haswell); else set_latency_gen4(); } diff --git a/src/mesa/drivers/dri/i965/brw_surface_formats.c b/src/mesa/drivers/dri/i965/brw_surface_formats.c index 660c3644964..f4feed4dc0b 100644 --- a/src/mesa/drivers/dri/i965/brw_surface_formats.c +++ b/src/mesa/drivers/dri/i965/brw_surface_formats.c @@ -533,7 +533,7 @@ brw_init_surface_formats(struct brw_context *brw) gl_format format; gen = intel->gen * 10; - if (intel->is_g4x) + if (brw->is_g4x) gen += 5; for (format = MESA_FORMAT_NONE + 1; format < MESA_FORMAT_COUNT; format++) { @@ -715,7 +715,7 @@ translate_tex_format(struct brw_context *brw, return BRW_SURFACEFORMAT_R32G32B32A32_FLOAT; case MESA_FORMAT_SRGB_DXT1: - if (intel->gen == 4 && !intel->is_g4x) { + if (intel->gen == 4 && !brw->is_g4x) { /* Work around missing SRGB DXT1 support on original gen4 by just * skipping SRGB decode. It's not worth not supporting sRGB in * general to prevent this. diff --git a/src/mesa/drivers/dri/i965/brw_urb.c b/src/mesa/drivers/dri/i965/brw_urb.c index 43b9ba4d4a6..3ac5573257a 100644 --- a/src/mesa/drivers/dri/i965/brw_urb.c +++ b/src/mesa/drivers/dri/i965/brw_urb.c @@ -158,7 +158,7 @@ static void recalculate_urb_fence( struct brw_context *brw ) brw->urb.nr_vs_entries = limits[VS].preferred_nr_entries; brw->urb.nr_sf_entries = limits[SF].preferred_nr_entries; } - } else if (intel->is_g4x) { + } else if (brw->is_g4x) { brw->urb.nr_vs_entries = 64; if (check_urb_layout(brw)) { goto done; diff --git a/src/mesa/drivers/dri/i965/brw_vec4_emit.cpp b/src/mesa/drivers/dri/i965/brw_vec4_emit.cpp index f15759ff0b3..b75155be8ac 100644 --- a/src/mesa/drivers/dri/i965/brw_vec4_emit.cpp +++ b/src/mesa/drivers/dri/i965/brw_vec4_emit.cpp @@ -281,7 +281,7 @@ vec4_generator::generate_tex(vec4_instruction *inst, case SHADER_OPCODE_TXD: if (inst->shadow_compare) { /* Gen7.5+. Otherwise, lowered by brw_lower_texture_gradients(). */ - assert(intel->is_haswell); + assert(brw->is_haswell); msg_type = HSW_SAMPLER_MESSAGE_SAMPLE_DERIV_COMPARE; } else { msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_DERIVS; @@ -457,7 +457,7 @@ vec4_generator::generate_scratch_read(vec4_instruction *inst, if (intel->gen >= 6) msg_type = GEN6_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ; - else if (intel->gen == 5 || intel->is_g4x) + else if (intel->gen == 5 || brw->is_g4x) msg_type = G45_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ; else msg_type = BRW_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ; @@ -575,7 +575,7 @@ vec4_generator::generate_pull_constant_load(vec4_instruction *inst, if (intel->gen >= 6) msg_type = GEN6_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ; - else if (intel->gen == 5 || intel->is_g4x) + else if (intel->gen == 5 || brw->is_g4x) msg_type = G45_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ; else msg_type = BRW_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ; diff --git a/src/mesa/drivers/dri/i965/brw_vs.c b/src/mesa/drivers/dri/i965/brw_vs.c index 292064ee376..03fc72019ea 100644 --- a/src/mesa/drivers/dri/i965/brw_vs.c +++ b/src/mesa/drivers/dri/i965/brw_vs.c @@ -456,7 +456,7 @@ static void brw_upload_vs_prog(struct brw_context *brw) brw_populate_sampler_prog_key_data(ctx, prog, &key.base.tex); /* BRW_NEW_VERTICES */ - if (intel->gen < 8 && !intel->is_haswell) { + if (intel->gen < 8 && !brw->is_haswell) { /* Prior to Haswell, the hardware can't natively support GL_FIXED or * 2_10_10_10_REV vertex formats. Set appropriate workaround flags. */ diff --git a/src/mesa/drivers/dri/i965/brw_vs_state.c b/src/mesa/drivers/dri/i965/brw_vs_state.c index 722afc536ee..fe832ced6fc 100644 --- a/src/mesa/drivers/dri/i965/brw_vs_state.c +++ b/src/mesa/drivers/dri/i965/brw_vs_state.c @@ -119,7 +119,7 @@ brw_upload_vs_unit(struct brw_context *brw) case 32: break; case 64: - assert(intel->is_g4x); + assert(brw->is_g4x); break; default: assert(0); diff --git a/src/mesa/drivers/dri/i965/brw_wm.c b/src/mesa/drivers/dri/i965/brw_wm.c index 603c63644c3..7ba0ee0265b 100644 --- a/src/mesa/drivers/dri/i965/brw_wm.c +++ b/src/mesa/drivers/dri/i965/brw_wm.c @@ -300,7 +300,7 @@ brw_populate_sampler_prog_key_data(struct gl_context *ctx, const struct gl_program *prog, struct brw_sampler_prog_key_data *key) { - struct intel_context *intel = intel_context(ctx); + struct brw_context *brw = brw_context(ctx); for (int s = 0; s < MAX_SAMPLERS; s++) { key->swizzles[s] = SWIZZLE_NOOP; @@ -323,7 +323,7 @@ brw_populate_sampler_prog_key_data(struct gl_context *ctx, /* Haswell handles texture swizzling as surface format overrides * (except for GL_ALPHA); all other platforms need MOVs in the shader. */ - if (!intel->is_haswell || alpha_depth) + if (!brw->is_haswell || alpha_depth) key->swizzles[s] = brw_get_texture_swizzle(ctx, t); if (img->InternalFormat == GL_YCBCR_MESA) { diff --git a/src/mesa/drivers/dri/i965/gen7_blorp.cpp b/src/mesa/drivers/dri/i965/gen7_blorp.cpp index 2d52211a4c2..102118f874c 100644 --- a/src/mesa/drivers/dri/i965/gen7_blorp.cpp +++ b/src/mesa/drivers/dri/i965/gen7_blorp.cpp @@ -132,8 +132,6 @@ gen7_blorp_emit_surface_state(struct brw_context *brw, uint32_t read_domains, uint32_t write_domain, bool is_render_target) { - struct intel_context *intel = &brw->intel; - uint32_t wm_surf_offset; uint32_t width = surface->width; uint32_t height = surface->height; @@ -194,7 +192,7 @@ gen7_blorp_emit_surface_state(struct brw_context *brw, surf[7] = surface->mt->fast_clear_color_value; - if (intel->is_haswell) { + if (brw->is_haswell) { surf[7] |= (SET_FIELD(HSW_SCS_RED, GEN7_SURFACE_SCS_R) | SET_FIELD(HSW_SCS_GREEN, GEN7_SURFACE_SCS_G) | SET_FIELD(HSW_SCS_BLUE, GEN7_SURFACE_SCS_B) | @@ -539,9 +537,8 @@ gen7_blorp_emit_ps_config(struct brw_context *brw, uint32_t prog_offset, brw_blorp_prog_data *prog_data) { - struct intel_context *intel = &brw->intel; uint32_t dw2, dw4, dw5; - const int max_threads_shift = brw->intel.is_haswell ? + const int max_threads_shift = brw->is_haswell ? HSW_PS_MAX_THREADS_SHIFT : IVB_PS_MAX_THREADS_SHIFT; dw2 = dw4 = dw5 = 0; @@ -555,7 +552,7 @@ gen7_blorp_emit_ps_config(struct brw_context *brw, */ dw4 |= GEN7_PS_16_DISPATCH_ENABLE; - if (intel->is_haswell) + if (brw->is_haswell) dw4 |= SET_FIELD(1, HSW_PS_SAMPLE_MASK); /* 1 sample for now */ if (params->use_wm_prog) { dw2 |= 1 << GEN7_PS_SAMPLER_COUNT_SHIFT; /* Up to 4 samplers */ diff --git a/src/mesa/drivers/dri/i965/gen7_misc_state.c b/src/mesa/drivers/dri/i965/gen7_misc_state.c index 9f40690e51a..4f6b20d6b3b 100644 --- a/src/mesa/drivers/dri/i965/gen7_misc_state.c +++ b/src/mesa/drivers/dri/i965/gen7_misc_state.c @@ -94,7 +94,7 @@ gen7_emit_depth_stencil_hiz(struct brw_context *brw, OUT_BATCH(0); ADVANCE_BATCH(); } else { - const int enabled = intel->is_haswell ? HSW_STENCIL_ENABLED : 0; + const int enabled = brw->is_haswell ? HSW_STENCIL_ENABLED : 0; BEGIN_BATCH(3); OUT_BATCH(GEN7_3DSTATE_STENCIL_BUFFER << 16 | (3 - 2)); diff --git a/src/mesa/drivers/dri/i965/gen7_sf_state.c b/src/mesa/drivers/dri/i965/gen7_sf_state.c index d72ee02ccf5..98526870a3c 100644 --- a/src/mesa/drivers/dri/i965/gen7_sf_state.c +++ b/src/mesa/drivers/dri/i965/gen7_sf_state.c @@ -258,7 +258,7 @@ upload_sf_state(struct brw_context *brw) dw2 |= GEN6_SF_LINE_AA_ENABLE; dw2 |= GEN6_SF_LINE_END_CAP_WIDTH_1_0; } - if (ctx->Line.StippleFlag && intel->is_haswell) { + if (ctx->Line.StippleFlag && brw->is_haswell) { dw2 |= HSW_SF_LINE_STIPPLE_ENABLE; } /* _NEW_MULTISAMPLE */ diff --git a/src/mesa/drivers/dri/i965/gen7_urb.c b/src/mesa/drivers/dri/i965/gen7_urb.c index 82eac5add90..862e8153f6e 100644 --- a/src/mesa/drivers/dri/i965/gen7_urb.c +++ b/src/mesa/drivers/dri/i965/gen7_urb.c @@ -59,7 +59,7 @@ gen7_allocate_push_constants(struct brw_context *brw) struct intel_context *intel = &brw->intel; unsigned size = 8; - if (intel->is_haswell && intel->gt == 3) + if (brw->is_haswell && intel->gt == 3) size = 16; BEGIN_BATCH(2); @@ -77,7 +77,7 @@ static void gen7_upload_urb(struct brw_context *brw) { struct intel_context *intel = &brw->intel; - const int push_size_kB = intel->is_haswell && intel->gt == 3 ? 32 : 16; + const int push_size_kB = brw->is_haswell && intel->gt == 3 ? 32 : 16; /* Total space for entries is URB size - 16kB for push constants */ int handle_region_size = (brw->urb.size - push_size_kB) * 1024; /* bytes */ diff --git a/src/mesa/drivers/dri/i965/gen7_vs_state.c b/src/mesa/drivers/dri/i965/gen7_vs_state.c index 6c16a9d4850..37e5c8b075b 100644 --- a/src/mesa/drivers/dri/i965/gen7_vs_state.c +++ b/src/mesa/drivers/dri/i965/gen7_vs_state.c @@ -34,7 +34,7 @@ upload_vs_state(struct brw_context *brw) { struct gl_context *ctx = &brw->intel.ctx; uint32_t floating_point_mode = 0; - const int max_threads_shift = brw->intel.is_haswell ? + const int max_threads_shift = brw->is_haswell ? HSW_VS_MAX_THREADS_SHIFT : GEN6_VS_MAX_THREADS_SHIFT; gen7_emit_vs_workaround_flush(brw); diff --git a/src/mesa/drivers/dri/i965/gen7_wm_state.c b/src/mesa/drivers/dri/i965/gen7_wm_state.c index 8ae7aeac873..a44766606a6 100644 --- a/src/mesa/drivers/dri/i965/gen7_wm_state.c +++ b/src/mesa/drivers/dri/i965/gen7_wm_state.c @@ -115,7 +115,7 @@ upload_ps_state(struct brw_context *brw) struct intel_context *intel = &brw->intel; struct gl_context *ctx = &intel->ctx; uint32_t dw2, dw4, dw5; - const int max_threads_shift = intel->is_haswell ? + const int max_threads_shift = brw->is_haswell ? HSW_PS_MAX_THREADS_SHIFT : IVB_PS_MAX_THREADS_SHIFT; /* BRW_NEW_PS_BINDING_TABLE */ @@ -172,7 +172,7 @@ upload_ps_state(struct brw_context *brw) if (ctx->Shader.CurrentFragmentProgram == NULL) dw2 |= GEN7_PS_FLOATING_POINT_MODE_ALT; - if (intel->is_haswell) + if (brw->is_haswell) dw4 |= SET_FIELD(1, HSW_PS_SAMPLE_MASK); /* 1 sample for now */ dw4 |= (brw->max_wm_threads - 1) << max_threads_shift; diff --git a/src/mesa/drivers/dri/i965/gen7_wm_surface_state.c b/src/mesa/drivers/dri/i965/gen7_wm_surface_state.c index ee1fe4ba3e7..e1690a79827 100644 --- a/src/mesa/drivers/dri/i965/gen7_wm_surface_state.c +++ b/src/mesa/drivers/dri/i965/gen7_wm_surface_state.c @@ -347,7 +347,7 @@ gen7_update_texture_surface(struct gl_context *ctx, /* mip count */ (intelObj->_MaxLevel - tObj->BaseLevel)); - if (intel->is_haswell) { + if (brw->is_haswell) { /* Handling GL_ALPHA as a surface format override breaks 1.30+ style * texturing functions that return a float, as our code generation always * selects the .x channel (which would always be 0). @@ -410,7 +410,7 @@ gen7_create_constant_surface(struct brw_context *brw, surf[3] = SET_FIELD((w >> 21) & 0x3f, BRW_SURFACE_DEPTH) | (stride - 1); - if (intel->is_haswell) { + if (brw->is_haswell) { surf[7] = SET_FIELD(HSW_SCS_RED, GEN7_SURFACE_SCS_R) | SET_FIELD(HSW_SCS_GREEN, GEN7_SURFACE_SCS_G) | SET_FIELD(HSW_SCS_BLUE, GEN7_SURFACE_SCS_B) | @@ -612,7 +612,7 @@ gen7_update_renderbuffer_surface(struct brw_context *brw, surf[7] = irb->mt->fast_clear_color_value; - if (intel->is_haswell) { + if (brw->is_haswell) { surf[7] |= (SET_FIELD(HSW_SCS_RED, GEN7_SURFACE_SCS_R) | SET_FIELD(HSW_SCS_GREEN, GEN7_SURFACE_SCS_G) | SET_FIELD(HSW_SCS_BLUE, GEN7_SURFACE_SCS_B) | diff --git a/src/mesa/drivers/dri/i965/intel_context.c b/src/mesa/drivers/dri/i965/intel_context.c index c1a7e0c32f5..a3c1042e5f8 100644 --- a/src/mesa/drivers/dri/i965/intel_context.c +++ b/src/mesa/drivers/dri/i965/intel_context.c @@ -487,12 +487,12 @@ intelInitContext(struct brw_context *brw, intel->gt = 0; if (IS_HASWELL(devID)) { - intel->is_haswell = true; + brw->is_haswell = true; } else if (IS_BAYTRAIL(devID)) { - intel->is_baytrail = true; + brw->is_baytrail = true; intel->gt = 1; } else if (IS_G4X(devID)) { - intel->is_g4x = true; + brw->is_g4x = true; } brw->has_separate_stencil = brw->intelScreen->hw_has_separate_stencil; diff --git a/src/mesa/drivers/dri/i965/intel_context.h b/src/mesa/drivers/dri/i965/intel_context.h index c9941011553..9194d0db04c 100644 --- a/src/mesa/drivers/dri/i965/intel_context.h +++ b/src/mesa/drivers/dri/i965/intel_context.h @@ -118,9 +118,6 @@ struct intel_context */ int gen; int gt; - bool is_haswell; - bool is_baytrail; - bool is_g4x; bool has_llc; }; diff --git a/src/mesa/drivers/dri/i965/intel_fbo.c b/src/mesa/drivers/dri/i965/intel_fbo.c index 9fbd12a68cf..02eca0aaf13 100644 --- a/src/mesa/drivers/dri/i965/intel_fbo.c +++ b/src/mesa/drivers/dri/i965/intel_fbo.c @@ -192,7 +192,6 @@ intel_alloc_renderbuffer_storage(struct gl_context * ctx, struct gl_renderbuffer GLuint width, GLuint height) { struct brw_context *brw = brw_context(ctx); - struct intel_context *intel = intel_context(ctx); struct intel_screen *screen = brw->intelScreen; struct intel_renderbuffer *irb = intel_renderbuffer(rb); rb->NumSamples = intel_quantize_num_samples(screen, rb->NumSamples); diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c index 579383567c5..a14b28796e5 100644 --- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c +++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c @@ -488,13 +488,12 @@ intel_miptree_create(struct brw_context *brw, GLuint num_samples, enum intel_miptree_tiling_mode requested_tiling) { - struct intel_context *intel = &brw->intel; struct intel_mipmap_tree *mt; gl_format tex_format = format; gl_format etc_format = MESA_FORMAT_NONE; GLuint total_width, total_height; - if (!intel->is_baytrail) { + if (!brw->is_baytrail) { switch (format) { case MESA_FORMAT_ETC1_RGB8: format = MESA_FORMAT_RGBX8888_REV; @@ -1248,10 +1247,9 @@ intel_miptree_slice_enable_hiz(struct brw_context *brw, uint32_t level, uint32_t layer) { - struct intel_context *intel = &brw->intel; assert(mt->hiz_mt); - if (intel->is_haswell) { + if (brw->is_haswell) { /* Disable HiZ for some slices to work around a hardware bug. * * Haswell hardware fails to respect |