diff options
Diffstat (limited to 'src')
-rw-r--r-- | src/mesa/drivers/dri/i965/brw_clip.c | 20 | ||||
-rw-r--r-- | src/mesa/drivers/dri/i965/brw_clip.h | 5 | ||||
-rw-r--r-- | src/mesa/drivers/dri/i965/brw_clip_tri.c | 5 | ||||
-rw-r--r-- | src/mesa/drivers/dri/i965/brw_clip_util.c | 13 |
4 files changed, 19 insertions, 24 deletions
diff --git a/src/mesa/drivers/dri/i965/brw_clip.c b/src/mesa/drivers/dri/i965/brw_clip.c index 96d278f1703..a1e9dae9154 100644 --- a/src/mesa/drivers/dri/i965/brw_clip.c +++ b/src/mesa/drivers/dri/i965/brw_clip.c @@ -55,6 +55,7 @@ static void compile_clip_prog( struct brw_context *brw, GLuint program_size; GLuint delta; GLuint i; + GLuint header_regs; memset(&c, 0, sizeof(c)); @@ -72,27 +73,28 @@ static void compile_clip_prog( struct brw_context *brw, c.header_position_offset = ATTR_SIZE; if (intel->gen == 5) - delta = 3 * REG_SIZE; + header_regs = 3; else - delta = REG_SIZE; + header_regs = 1; - for (i = 0; i < VERT_RESULT_MAX; i++) + delta = header_regs * REG_SIZE; + + for (i = 0; i < VERT_RESULT_MAX; i++) { if (c.key.attrs & BITFIELD64_BIT(i)) { c.offset[i] = delta; delta += ATTR_SIZE; - } - c.nr_attrs = brw_count_bits(c.key.attrs); + c.idx_to_attr[c.nr_attrs] = i; + c.nr_attrs++; + } + } /* The vertex attributes start at a URB row-aligned offset after * the 8-20 dword vertex header, and continue for a URB row-aligned * length. nr_regs determines the urb_read_length from the start * of the header to the end of the vertex data. */ - if (intel->gen == 5) - c.nr_regs = 3 + (c.nr_attrs + 1) / 2; - else - c.nr_regs = 1 + (c.nr_attrs + 1) / 2; + c.nr_regs = header_regs + (c.nr_attrs + 1) / 2; c.nr_bytes = c.nr_regs * REG_SIZE; diff --git a/src/mesa/drivers/dri/i965/brw_clip.h b/src/mesa/drivers/dri/i965/brw_clip.h index 68222c6c278..3a8cd7bf390 100644 --- a/src/mesa/drivers/dri/i965/brw_clip.h +++ b/src/mesa/drivers/dri/i965/brw_clip.h @@ -115,7 +115,10 @@ struct brw_clip_compile { GLboolean need_direction; GLuint header_position_offset; - GLuint offset[VERT_ATTRIB_MAX]; + /** Mapping from VERT_RESULT_* to offset within the VUE. */ + GLuint offset[VERT_RESULT_MAX]; + /** Mapping from attribute index to VERT_RESULT_* */ + GLuint idx_to_attr[VERT_RESULT_MAX]; }; #define ATTR_SIZE (4*4) diff --git a/src/mesa/drivers/dri/i965/brw_clip_tri.c b/src/mesa/drivers/dri/i965/brw_clip_tri.c index fd425b39ad6..cb58d1da9fe 100644 --- a/src/mesa/drivers/dri/i965/brw_clip_tri.c +++ b/src/mesa/drivers/dri/i965/brw_clip_tri.c @@ -76,10 +76,7 @@ void brw_clip_tri_alloc_regs( struct brw_clip_compile *c, if (c->nr_attrs & 1) { for (j = 0; j < 3; j++) { - GLuint delta = c->nr_attrs*16 + 32; - - if (intel->gen == 5) - delta = c->nr_attrs * 16 + 32 * 3; + GLuint delta = c->offset[c->idx_to_attr[c->nr_attrs - 1]] + ATTR_SIZE; brw_MOV(&c->func, byte_offset(c->reg.vertex[j], delta), brw_imm_f(0)); } diff --git a/src/mesa/drivers/dri/i965/brw_clip_util.c b/src/mesa/drivers/dri/i965/brw_clip_util.c index 9708d7e6186..a74bbc25643 100644 --- a/src/mesa/drivers/dri/i965/brw_clip_util.c +++ b/src/mesa/drivers/dri/i965/brw_clip_util.c @@ -134,7 +134,6 @@ void brw_clip_interp_vertex( struct brw_clip_compile *c, GLboolean force_edgeflag) { struct brw_compile *p = &c->func; - struct intel_context *intel = &p->brw->intel; struct brw_reg tmp = get_tmp(c); GLuint i; @@ -149,12 +148,9 @@ void brw_clip_interp_vertex( struct brw_clip_compile *c, /* Iterate over each attribute (could be done in pairs?) */ for (i = 0; i < c->nr_attrs; i++) { - GLuint delta = i*16 + 32; + GLuint delta = c->offset[c->idx_to_attr[i]]; - if (intel->gen == 5) - delta = i * 16 + 32 * 3; - - if (delta == c->offset[VERT_RESULT_EDGE]) { + if (c->idx_to_attr[i] == VERT_RESULT_EDGE) { if (force_edgeflag) brw_MOV(p, deref_4f(dest_ptr, delta), brw_imm_f(1)); else @@ -183,10 +179,7 @@ void brw_clip_interp_vertex( struct brw_clip_compile *c, } if (i & 1) { - GLuint delta = i*16 + 32; - - if (intel->gen == 5) - delta = i * 16 + 32 * 3; + GLuint delta = c->offset[c->idx_to_attr[c->nr_attrs - 1]] + ATTR_SIZE; brw_MOV(p, deref_4f(dest_ptr, delta), brw_imm_f(0)); } |