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-rw-r--r--src/mesa/drivers/dri/i965/Makefile.sources3
-rw-r--r--src/mesa/drivers/dri/i965/brw_blorp.c10
-rw-r--r--src/mesa/drivers/dri/i965/brw_blorp.h6
-rw-r--r--src/mesa/drivers/dri/i965/brw_context.c3
-rw-r--r--src/mesa/drivers/dri/i965/gen4_blorp_exec.h197
-rw-r--r--src/mesa/drivers/dri/i965/genX_blorp_exec.c11
6 files changed, 227 insertions, 3 deletions
diff --git a/src/mesa/drivers/dri/i965/Makefile.sources b/src/mesa/drivers/dri/i965/Makefile.sources
index 37338167c98..cc030c2adeb 100644
--- a/src/mesa/drivers/dri/i965/Makefile.sources
+++ b/src/mesa/drivers/dri/i965/Makefile.sources
@@ -126,12 +126,15 @@ i965_FILES = \
libdrm_macros.h
i965_gen4_FILES = \
+ genX_blorp_exec.c \
genX_state_upload.c
i965_gen45_FILES = \
+ genX_blorp_exec.c \
genX_state_upload.c
i965_gen5_FILES = \
+ genX_blorp_exec.c \
genX_state_upload.c
i965_gen6_FILES = \
diff --git a/src/mesa/drivers/dri/i965/brw_blorp.c b/src/mesa/drivers/dri/i965/brw_blorp.c
index 64aa4c90883..7404606b9b6 100644
--- a/src/mesa/drivers/dri/i965/brw_blorp.c
+++ b/src/mesa/drivers/dri/i965/brw_blorp.c
@@ -71,6 +71,16 @@ brw_blorp_init(struct brw_context *brw)
brw->blorp.compiler = brw->screen->compiler;
switch (brw->gen) {
+ case 4:
+ if (brw->is_g4x) {
+ brw->blorp.exec = gen45_blorp_exec;
+ } else {
+ brw->blorp.exec = gen4_blorp_exec;
+ }
+ break;
+ case 5:
+ brw->blorp.exec = gen5_blorp_exec;
+ break;
case 6:
brw->blorp.mocs.tex = 0;
brw->blorp.mocs.rb = 0;
diff --git a/src/mesa/drivers/dri/i965/brw_blorp.h b/src/mesa/drivers/dri/i965/brw_blorp.h
index ee4bf3bf541..8743d963abc 100644
--- a/src/mesa/drivers/dri/i965/brw_blorp.h
+++ b/src/mesa/drivers/dri/i965/brw_blorp.h
@@ -72,6 +72,12 @@ void
intel_hiz_exec(struct brw_context *brw, struct intel_mipmap_tree *mt,
unsigned int level, unsigned int layer, enum blorp_hiz_op op);
+void gen4_blorp_exec(struct blorp_batch *batch,
+ const struct blorp_params *params);
+void gen45_blorp_exec(struct blorp_batch *batch,
+ const struct blorp_params *params);
+void gen5_blorp_exec(struct blorp_batch *batch,
+ const struct blorp_params *params);
void gen6_blorp_exec(struct blorp_batch *batch,
const struct blorp_params *params);
void gen7_blorp_exec(struct blorp_batch *batch,
diff --git a/src/mesa/drivers/dri/i965/brw_context.c b/src/mesa/drivers/dri/i965/brw_context.c
index d3ed871618c..c815a0454d7 100644
--- a/src/mesa/drivers/dri/i965/brw_context.c
+++ b/src/mesa/drivers/dri/i965/brw_context.c
@@ -1118,8 +1118,7 @@ brwCreateContext(gl_api api,
brw_init_surface_formats(brw);
- if (brw->gen >= 6)
- brw_blorp_init(brw);
+ brw_blorp_init(brw);
brw->urb.size = devinfo->urb.size;
diff --git a/src/mesa/drivers/dri/i965/gen4_blorp_exec.h b/src/mesa/drivers/dri/i965/gen4_blorp_exec.h
new file mode 100644
index 00000000000..183c0da0af3
--- /dev/null
+++ b/src/mesa/drivers/dri/i965/gen4_blorp_exec.h
@@ -0,0 +1,197 @@
+/*
+ * Copyright © 2016 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ */
+
+static inline struct blorp_address
+dynamic_state_address(struct blorp_batch *batch, uint32_t offset)
+{
+ assert(batch->blorp->driver_ctx == batch->driver_batch);
+ struct brw_context *brw = batch->driver_batch;
+
+ return (struct blorp_address) {
+ .buffer = brw->batch.bo,
+ .offset = offset,
+ .write_domain = 0,
+ .read_domains = I915_GEM_DOMAIN_INSTRUCTION,
+ };
+}
+
+static inline struct blorp_address
+instruction_state_address(struct blorp_batch *batch, uint32_t offset)
+{
+ assert(batch->blorp->driver_ctx == batch->driver_batch);
+ struct brw_context *brw = batch->driver_batch;
+
+ return (struct blorp_address) {
+ .buffer = brw->cache.bo,
+ .offset = offset,
+ .write_domain = 0,
+ .read_domains = I915_GEM_DOMAIN_INSTRUCTION,
+ };
+}
+
+static struct blorp_address
+blorp_emit_vs_state(struct blorp_batch *batch,
+ const struct blorp_params *params)
+{
+ assert(batch->blorp->driver_ctx == batch->driver_batch);
+ struct brw_context *brw = batch->driver_batch;
+
+ uint32_t offset;
+ blorp_emit_dynamic(batch, GENX(VS_STATE), vs, 64, &offset) {
+ vs.Enable = false;
+ vs.URBEntryAllocationSize = brw->urb.vsize - 1;
+#if GEN_GEN == 5
+ vs.NumberofURBEntries = brw->urb.nr_vs_entries >> 2;
+#else
+ vs.NumberofURBEntries = brw->urb.nr_vs_entries;
+#endif
+ }
+
+ return dynamic_state_address(batch, offset);
+}
+
+static struct blorp_address
+blorp_emit_sf_state(struct blorp_batch *batch,
+ const struct blorp_params *params)
+{
+ assert(batch->blorp->driver_ctx == batch->driver_batch);
+ struct brw_context *brw = batch->driver_batch;
+ const struct brw_sf_prog_data *prog_data = params->sf_prog_data;
+
+ uint32_t offset;
+ blorp_emit_dynamic(batch, GENX(SF_STATE), sf, 64, &offset) {
+#if GEN_GEN == 4
+ sf.KernelStartPointer =
+ instruction_state_address(batch, params->sf_prog_kernel);
+#else
+ sf.KernelStartPointer = params->sf_prog_kernel;
+#endif
+ sf.GRFRegisterCount = DIV_ROUND_UP(prog_data->total_grf, 16) - 1;
+ sf.VertexURBEntryReadLength = prog_data->urb_read_length;
+ sf.VertexURBEntryReadOffset = BRW_SF_URB_ENTRY_READ_OFFSET;
+ sf.DispatchGRFStartRegisterForURBData = 3;
+
+ sf.URBEntryAllocationSize = brw->urb.sfsize - 1;
+ sf.NumberofURBEntries = brw->urb.nr_sf_entries;
+
+#if GEN_GEN == 5
+ sf.MaximumNumberofThreads = MIN2(48, brw->urb.nr_sf_entries) - 1;
+#else
+ sf.MaximumNumberofThreads = MIN2(24, brw->urb.nr_sf_entries) - 1;
+#endif
+
+ sf.ViewportTransformEnable = false;
+
+ sf.CullMode = CULLMODE_NONE;
+ }
+
+ return dynamic_state_address(batch, offset);
+}
+
+static struct blorp_address
+blorp_emit_wm_state(struct blorp_batch *batch,
+ const struct blorp_params *params)
+{
+ const struct brw_wm_prog_data *prog_data = params->wm_prog_data;
+
+ uint32_t offset;
+ blorp_emit_dynamic(batch, GENX(WM_STATE), wm, 64, &offset) {
+ if (params->src.enabled) {
+ /* Iron Lake can't do sampler prefetch */
+ wm.SamplerCount = (GEN_GEN != 5);
+ wm.BindingTableEntryCount = 2;
+ uint32_t sampler = blorp_emit_sampler_state(batch, params);
+ wm.SamplerStatePointer = dynamic_state_address(batch, sampler);
+ }
+
+ if (prog_data) {
+ wm.DispatchGRFStartRegisterForURBData =
+ prog_data->base.dispatch_grf_start_reg;
+ wm.SetupURBEntryReadLength = prog_data->num_varying_inputs * 2;
+ wm.SetupURBEntryReadOffset = 0;
+
+ wm.DepthCoefficientURBReadOffset = 1;
+ wm.PixelShaderKillPixel = prog_data->uses_kill;
+ wm.ThreadDispatchEnable = true;
+ wm.EarlyDepthTestEnable = true;
+
+ wm._8PixelDispatchEnable = prog_data->dispatch_8;
+ wm._16PixelDispatchEnable = prog_data->dispatch_16;
+
+#if GEN_GEN == 4
+ wm.KernelStartPointer =
+ instruction_state_address(batch, params->wm_prog_kernel);
+ wm.GRFRegisterCount = prog_data->reg_blocks_0;
+#else
+ wm.KernelStartPointer0 = params->wm_prog_kernel;
+ wm.GRFRegisterCount0 = prog_data->reg_blocks_0;
+ wm.KernelStartPointer2 =
+ params->wm_prog_kernel + prog_data->prog_offset_2;
+ wm.GRFRegisterCount2 = prog_data->reg_blocks_2;
+#endif
+ }
+
+ wm.MaximumNumberofThreads =
+ batch->blorp->compiler->devinfo->max_wm_threads - 1;
+ }
+
+ return dynamic_state_address(batch, offset);
+}
+
+static struct blorp_address
+blorp_emit_color_calc_state(struct blorp_batch *batch,
+ const struct blorp_params *params)
+{
+ uint32_t cc_viewport = blorp_emit_cc_viewport(batch, params);
+
+ uint32_t offset;
+ blorp_emit_dynamic(batch, GENX(COLOR_CALC_STATE), cc, 64, &offset) {
+ cc.CCViewportStatePointer = dynamic_state_address(batch, cc_viewport);
+ }
+
+ return dynamic_state_address(batch, offset);
+}
+
+static void
+blorp_emit_pipeline(struct blorp_batch *batch,
+ const struct blorp_params *params)
+{
+ assert(batch->blorp->driver_ctx == batch->driver_batch);
+ struct brw_context *brw = batch->driver_batch;
+
+ emit_urb_config(batch, params);
+
+ blorp_emit(batch, GENX(3DSTATE_PIPELINED_POINTERS), pp) {
+ pp.PointertoVSState = blorp_emit_vs_state(batch, params);
+ pp.GSEnable = false;
+ pp.ClipEnable = false;
+ pp.PointertoSFState = blorp_emit_sf_state(batch, params);
+ pp.PointertoWMState = blorp_emit_wm_state(batch, params);
+ pp.PointertoColorCalcState = blorp_emit_color_calc_state(batch, params);
+ }
+
+ brw_upload_urb_fence(brw);
+
+ blorp_emit(batch, GENX(CS_URB_STATE), curb);
+ blorp_emit(batch, GENX(CONSTANT_BUFFER), curb);
+}
diff --git a/src/mesa/drivers/dri/i965/genX_blorp_exec.c b/src/mesa/drivers/dri/i965/genX_blorp_exec.c
index 72ac274d2f5..3451d7187eb 100644
--- a/src/mesa/drivers/dri/i965/genX_blorp_exec.c
+++ b/src/mesa/drivers/dri/i965/genX_blorp_exec.c
@@ -32,6 +32,10 @@
#include "blorp/blorp_genX_exec.h"
+#if GEN_GEN <= 5
+#include "gen4_blorp_exec.h"
+#endif
+
#include "brw_blorp.h"
static void *
@@ -169,8 +173,11 @@ blorp_emit_urb_config(struct blorp_batch *batch,
brw->ctx.NewDriverState |= BRW_NEW_URB_SIZE;
gen7_upload_urb(brw, vs_entry_size, false, false);
-#else
+#elif GEN_GEN == 6
gen6_upload_urb(brw, vs_entry_size, false, 0);
+#else
+ /* We calculate it now and emit later. */
+ brw_calculate_urb_fence(brw, 0, vs_entry_size, sf_entry_size);
#endif
}
@@ -215,7 +222,9 @@ retry:
gen7_l3_state.emit(brw);
#endif
+#if GEN_GEN >= 6
brw_emit_depth_stall_flushes(brw);
+#endif
#if GEN_GEN == 8
gen8_write_pma_stall_bits(brw, 0);
generated by cgit v1.2.3 (git 2.39.1) at 2024-12-02 15:34:45 +0000