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-rw-r--r--src/mesa/drivers/dri/radeon/radeon_mipmap_tree.c27
1 files changed, 7 insertions, 20 deletions
diff --git a/src/mesa/drivers/dri/radeon/radeon_mipmap_tree.c b/src/mesa/drivers/dri/radeon/radeon_mipmap_tree.c
index 033f26db2a1..a1a523931fb 100644
--- a/src/mesa/drivers/dri/radeon/radeon_mipmap_tree.c
+++ b/src/mesa/drivers/dri/radeon/radeon_mipmap_tree.c
@@ -177,6 +177,12 @@ static void calculate_miptree_layout_r300(radeonContextPtr rmesa, radeon_mipmap_
for(face = 0; face < mt->faces; face++)
compute_tex_image_offset(rmesa, mt, face, level, &curOffset);
+ /* r600 cube levels seems to be aligned to 8 faces but
+ * we have separate register for 1'st level offset so add
+ * 2 image alignment after 1'st mip level */
+ if(rmesa->radeonScreen->chip_family >= CHIP_FAMILY_R600 &&
+ mt->target == GL_TEXTURE_CUBE_MAP && level >= 1)
+ curOffset += 2 * mt->levels[level].size;
}
/* Note the required size in memory */
@@ -380,25 +386,6 @@ void radeon_try_alloc_miptree(radeonContextPtr rmesa, radeonTexObj *t)
texImg->Depth, t->tile_bits);
}
-/* Although we use the image_offset[] array to store relative offsets
- * to cube faces, Mesa doesn't know anything about this and expects
- * each cube face to be treated as a separate image.
- *
- * These functions present that view to mesa:
- */
-void
-radeon_miptree_depth_offsets(radeon_mipmap_tree *mt, GLuint level, GLuint *offsets)
-{
- if (mt->target != GL_TEXTURE_3D || mt->faces == 1) {
- offsets[0] = 0;
- } else {
- int i;
- for (i = 0; i < 6; i++) {
- offsets[i] = mt->levels[level].faces[i].offset;
- }
- }
-}
-
GLuint
radeon_miptree_image_offset(radeon_mipmap_tree *mt,
GLuint face, GLuint level)
@@ -619,4 +606,4 @@ uint32_t get_base_teximage_offset(radeonTexObj *texObj)
} else {
return radeon_miptree_image_offset(texObj->mt, 0, texObj->minLod);
}
-} \ No newline at end of file
+}