1 files changed, 39 insertions, 18 deletions

diff --git a/src/mesa/drivers/dri/r300/r300_cmdbuf.c b/src/mesa/drivers/dri/r300/r300_cmdbuf.c
index 0261a5b1d8a..af535037d06 100644
--- a/src/mesa/drivers/dri/r300/r300_cmdbuf.c
+++ b/src/mesa/drivers/dri/r300/r300_cmdbuf.c
@@ -232,8 +232,8 @@ void r300_emit_scissor(GLcontext *ctx)
     } else {
         x1 = 0;
         y1 = 0;
-        x2 = rrb->width - 1;
-        y2 = rrb->height - 1;
+        x2 = rrb->base.Width - 1;
+        y2 = rrb->base.Height - 1;
     }
     if (r300->radeon.radeonScreen->chip_family < CHIP_FAMILY_RV515) {
         x1 += R300_SCISSORS_OFFSET;
@@ -264,11 +264,22 @@ static void emit_cb_offset(GLcontext *ctx, struct radeon_state_atom * atom)
 		return;
 	}
 
+        if (RADEON_DEBUG & DEBUG_STATE)
+           fprintf(stderr,"rrb is %p %d %dx%d\n", rrb, offset, rrb->base.Width, rrb->base.Height);
 	cbpitch = (rrb->pitch / rrb->cpp);
 	if (rrb->cpp == 4)
 		cbpitch |= R300_COLOR_FORMAT_ARGB8888;
-	else
+	else switch (rrb->base._ActualFormat) {
+	case GL_RGB5:
 		cbpitch |= R300_COLOR_FORMAT_RGB565;
+		break;
+	case GL_RGBA4:
+		cbpitch |= R300_COLOR_FORMAT_ARGB4444;
+		break;
+	case GL_RGB5_A1:
+		cbpitch |= R300_COLOR_FORMAT_ARGB1555;
+		break;
+	}
 
 	if (rrb->bo->flags & RADEON_BO_FLAGS_MACRO_TILE)
 		cbpitch |= R300_COLOR_TILE_ENABLE;
@@ -289,14 +300,14 @@ static void emit_cb_offset(GLcontext *ctx, struct radeon_state_atom * atom)
             BEGIN_BATCH_NO_AUTOSTATE(3);
             OUT_BATCH_REGSEQ(R300_SC_SCISSORS_TL, 2);
             OUT_BATCH(0);
-            OUT_BATCH(((rrb->width - 1) << R300_SCISSORS_X_SHIFT) |
-                    ((rrb->height - 1) << R300_SCISSORS_Y_SHIFT));
+            OUT_BATCH(((rrb->base.Width - 1) << R300_SCISSORS_X_SHIFT) |
+                    ((rrb->base.Height - 1) << R300_SCISSORS_Y_SHIFT));
             END_BATCH();
             BEGIN_BATCH_NO_AUTOSTATE(16);
             for (i = 0; i < 4; i++) {
                 OUT_BATCH_REGSEQ(R300_SC_CLIPRECT_TL_0 + (i * 8), 2);
                 OUT_BATCH((0 << R300_CLIPRECT_X_SHIFT) | (0 << R300_CLIPRECT_Y_SHIFT));
-                OUT_BATCH(((rrb->width - 1) << R300_CLIPRECT_X_SHIFT) | ((rrb->height - 1) << R300_CLIPRECT_Y_SHIFT));
+                OUT_BATCH(((rrb->base.Width - 1) << R300_CLIPRECT_X_SHIFT) | ((rrb->base.Height - 1) << R300_CLIPRECT_Y_SHIFT));
             }
             OUT_BATCH_REGSEQ(R300_SC_CLIP_RULE, 1);
             OUT_BATCH(0xAAAA);
@@ -308,15 +319,15 @@ static void emit_cb_offset(GLcontext *ctx, struct radeon_state_atom * atom)
             OUT_BATCH_REGSEQ(R300_SC_SCISSORS_TL, 2);
             OUT_BATCH((R300_SCISSORS_OFFSET << R300_SCISSORS_X_SHIFT) |
                     (R300_SCISSORS_OFFSET << R300_SCISSORS_Y_SHIFT));
-            OUT_BATCH(((rrb->width + R300_SCISSORS_OFFSET - 1) << R300_SCISSORS_X_SHIFT) |
-                    ((rrb->height + R300_SCISSORS_OFFSET - 1) << R300_SCISSORS_Y_SHIFT));
+            OUT_BATCH(((rrb->base.Width + R300_SCISSORS_OFFSET - 1) << R300_SCISSORS_X_SHIFT) |
+                    ((rrb->base.Height + R300_SCISSORS_OFFSET - 1) << R300_SCISSORS_Y_SHIFT));
             END_BATCH();
             BEGIN_BATCH_NO_AUTOSTATE(16);
             for (i = 0; i < 4; i++) {
                 OUT_BATCH_REGSEQ(R300_SC_CLIPRECT_TL_0 + (i * 8), 2);
                 OUT_BATCH((R300_SCISSORS_OFFSET << R300_CLIPRECT_X_SHIFT) | (R300_SCISSORS_OFFSET << R300_CLIPRECT_Y_SHIFT));
-                OUT_BATCH(((R300_SCISSORS_OFFSET + rrb->width - 1) << R300_CLIPRECT_X_SHIFT) |
-                          ((R300_SCISSORS_OFFSET + rrb->height - 1) << R300_CLIPRECT_Y_SHIFT));
+                OUT_BATCH(((R300_SCISSORS_OFFSET + rrb->base.Width - 1) << R300_CLIPRECT_X_SHIFT) |
+                          ((R300_SCISSORS_OFFSET + rrb->base.Height - 1) << R300_CLIPRECT_Y_SHIFT));
             }
             OUT_BATCH_REGSEQ(R300_SC_CLIP_RULE, 1);
             OUT_BATCH(0xAAAA);
@@ -333,23 +344,33 @@ static void emit_zb_offset(GLcontext *ctx, struct radeon_state_atom * atom)
 	BATCH_LOCALS(&r300->radeon);
 	struct radeon_renderbuffer *rrb;
 	uint32_t zbpitch;
+	uint32_t dw;
 
 	rrb = radeon_get_depthbuffer(&r300->radeon);
 	if (!rrb)
 		return;
 
 	zbpitch = (rrb->pitch / rrb->cpp);
-	if (rrb->bo->flags & RADEON_BO_FLAGS_MACRO_TILE) {
-		zbpitch |= R300_DEPTHMACROTILE_ENABLE;
-	}
-	if (rrb->bo->flags & RADEON_BO_FLAGS_MICRO_TILE){
-		zbpitch |= R300_DEPTHMICROTILE_TILED;
+	if (!r300->radeon.radeonScreen->kernel_mm) {
+	    if (rrb->bo->flags & RADEON_BO_FLAGS_MACRO_TILE) {
+	        zbpitch |= R300_DEPTHMACROTILE_ENABLE;
+	   }
+	    if (rrb->bo->flags & RADEON_BO_FLAGS_MICRO_TILE){
+	        zbpitch |= R300_DEPTHMICROTILE_TILED;
+	    }
 	}
 
-	BEGIN_BATCH_NO_AUTOSTATE(6);
+	dw = 6;
+    	if (r300->radeon.radeonScreen->kernel_mm)
+		dw += 2;
+	BEGIN_BATCH_NO_AUTOSTATE(dw);
 	OUT_BATCH_REGSEQ(R300_ZB_DEPTHOFFSET, 1);
 	OUT_BATCH_RELOC(0, rrb->bo, 0, 0, RADEON_GEM_DOMAIN_VRAM, 0);
-	OUT_BATCH_REGVAL(R300_ZB_DEPTHPITCH, zbpitch);
+	OUT_BATCH_REGSEQ(R300_ZB_DEPTHPITCH, 1);
+    	if (!r300->radeon.radeonScreen->kernel_mm)
+	    OUT_BATCH(zbpitch);
+	else
+	    OUT_BATCH_RELOC(cbpitch, rrb->bo, zbpitch, 0, RADEON_GEM_DOMAIN_VRAM, 0);
 	END_BATCH();
 }
 
@@ -503,7 +524,7 @@ void r300InitCmdBuf(r300ContextPtr r300)
 	r300->hw.vap_cntl.cmd[R300_VAP_CNTL_FLUSH] = cmdpacket0(r300->radeon.radeonScreen, R300_VAP_PVS_STATE_FLUSH_REG, 1);
 	r300->hw.vap_cntl.cmd[R300_VAP_CNTL_FLUSH_1] = 0;
 	r300->hw.vap_cntl.cmd[R300_VAP_CNTL_CMD] = cmdpacket0(r300->radeon.radeonScreen, R300_VAP_CNTL, 1);
-	if (is_r500) {
+	if (is_r500 && !r300->radeon.radeonScreen->kernel_mm) {
 	    ALLOC_STATE(vap_index_offset, always, 2, 0);
 	    r300->hw.vap_index_offset.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R500_VAP_INDEX_OFFSET, 1);
 	    r300->hw.vap_index_offset.cmd[1] = 0;