diff options
Diffstat (limited to 'src/intel/vulkan/genX_gpu_memcpy.c')
| -rw-r--r-- | src/intel/vulkan/genX_gpu_memcpy.c | 35 |
1 files changed, 14 insertions, 21 deletions
diff --git a/src/intel/vulkan/genX_gpu_memcpy.c b/src/intel/vulkan/genX_gpu_memcpy.c index a8e99d1a695..2e35964d0c9 100644 --- a/src/intel/vulkan/genX_gpu_memcpy.c +++ b/src/intel/vulkan/genX_gpu_memcpy.c @@ -53,14 +53,13 @@ gcd_pow2_u64(uint64_t a, uint64_t b) void genX(cmd_buffer_mi_memcpy)(struct anv_cmd_buffer *cmd_buffer, - struct anv_bo *dst, uint32_t dst_offset, - struct anv_bo *src, uint32_t src_offset, + struct anv_address dst, struct anv_address src, uint32_t size) { /* This memcpy operates in units of dwords. */ assert(size % 4 == 0); - assert(dst_offset % 4 == 0); - assert(src_offset % 4 == 0); + assert(dst.offset % 4 == 0); + assert(src.offset % 4 == 0); #if GEN_GEN == 7 /* On gen7, the combination of commands used here(MI_LOAD_REGISTER_MEM @@ -85,14 +84,10 @@ genX(cmd_buffer_mi_memcpy)(struct anv_cmd_buffer *cmd_buffer, #endif for (uint32_t i = 0; i < size; i += 4) { - const struct anv_address src_addr = - (struct anv_address) { src, src_offset + i}; - const struct anv_address dst_addr = - (struct anv_address) { dst, dst_offset + i}; #if GEN_GEN >= 8 anv_batch_emit(&cmd_buffer->batch, GENX(MI_COPY_MEM_MEM), cp) { - cp.DestinationMemoryAddress = dst_addr; - cp.SourceMemoryAddress = src_addr; + cp.DestinationMemoryAddress = anv_address_add(dst, i); + cp.SourceMemoryAddress = anv_address_add(src, i); } #else /* IVB does not have a general purpose register for command streamer @@ -101,11 +96,11 @@ genX(cmd_buffer_mi_memcpy)(struct anv_cmd_buffer *cmd_buffer, #define TEMP_REG 0x2440 /* GEN7_3DPRIM_BASE_VERTEX */ anv_batch_emit(&cmd_buffer->batch, GENX(MI_LOAD_REGISTER_MEM), load) { load.RegisterAddress = TEMP_REG; - load.MemoryAddress = src_addr; + load.MemoryAddress = anv_address_add(src, i); } anv_batch_emit(&cmd_buffer->batch, GENX(MI_STORE_REGISTER_MEM), store) { store.RegisterAddress = TEMP_REG; - store.MemoryAddress = dst_addr; + store.MemoryAddress = anv_address_add(dst, i); } #undef TEMP_REG #endif @@ -115,15 +110,14 @@ genX(cmd_buffer_mi_memcpy)(struct anv_cmd_buffer *cmd_buffer, void genX(cmd_buffer_so_memcpy)(struct anv_cmd_buffer *cmd_buffer, - struct anv_bo *dst, uint32_t dst_offset, - struct anv_bo *src, uint32_t src_offset, + struct anv_address dst, struct anv_address src, uint32_t size) { if (size == 0) return; - assert(dst_offset + size <= dst->size); - assert(src_offset + size <= src->size); + assert(dst.offset + size <= dst.bo->size); + assert(src.offset + size <= src.bo->size); /* The maximum copy block size is 4 32-bit components at a time. */ unsigned bs = 16; @@ -156,14 +150,14 @@ genX(cmd_buffer_so_memcpy)(struct anv_cmd_buffer *cmd_buffer, &(struct GENX(VERTEX_BUFFER_STATE)) { .VertexBufferIndex = 32, /* Reserved for this */ .AddressModifyEnable = true, - .BufferStartingAddress = { src, src_offset }, + .BufferStartingAddress = src, .BufferPitch = bs, #if (GEN_GEN >= 8) .MemoryObjectControlState = GENX(MOCS), .BufferSize = size, #else .VertexBufferMemoryObjectControlState = GENX(MOCS), - .EndAddress = { src, src_offset + size - 1 }, + .EndAddress = anv_address_add(src, size - 1), #endif }); @@ -220,15 +214,14 @@ genX(cmd_buffer_so_memcpy)(struct anv_cmd_buffer *cmd_buffer, anv_batch_emit(&cmd_buffer->batch, GENX(3DSTATE_SO_BUFFER), sob) { sob.SOBufferIndex = 0; sob.SOBufferObjectControlState = GENX(MOCS); - sob.SurfaceBaseAddress = (struct anv_address) { dst, dst_offset }; + sob.SurfaceBaseAddress = dst; #if GEN_GEN >= 8 sob.SOBufferEnable = true; sob.SurfaceSize = size / 4 - 1; #else sob.SurfacePitch = bs; - sob.SurfaceEndAddress = sob.SurfaceBaseAddress; - sob.SurfaceEndAddress.offset += size; + sob.SurfaceEndAddress = anv_address_add(dst, size); #endif #if GEN_GEN >= 8 |