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-rw-r--r--src/intel/compiler/brw_eu_emit.c47
1 files changed, 47 insertions, 0 deletions
diff --git a/src/intel/compiler/brw_eu_emit.c b/src/intel/compiler/brw_eu_emit.c
index 0847d9b404c..0cbc682ebcf 100644
--- a/src/intel/compiler/brw_eu_emit.c
+++ b/src/intel/compiler/brw_eu_emit.c
@@ -2801,6 +2801,53 @@ brw_untyped_atomic(struct brw_codegen *p,
}
static uint32_t
+brw_dp_untyped_atomic_float_desc(struct brw_codegen *p,
+ unsigned atomic_op,
+ bool response_expected)
+{
+ const struct gen_device_info *devinfo = p->devinfo;
+ const unsigned msg_type = GEN9_DATAPORT_DC_PORT1_UNTYPED_ATOMIC_FLOAT_OP;
+ unsigned msg_control =
+ atomic_op | /* Atomic Operation Type: BRW_AOP_F* */
+ (response_expected ? 1 << 5 : 0); /* Return data expected */
+
+ assert(devinfo->gen >= 9);
+ assert(brw_get_default_access_mode(p) == BRW_ALIGN_1);
+
+ if (brw_get_default_exec_size(p) != BRW_EXECUTE_16)
+ msg_control |= 1 << 4; /* SIMD8 mode */
+
+ return brw_dp_surface_desc(devinfo, msg_type, msg_control);
+}
+
+void
+brw_untyped_atomic_float(struct brw_codegen *p,
+ struct brw_reg dst,
+ struct brw_reg payload,
+ struct brw_reg surface,
+ unsigned atomic_op,
+ unsigned msg_length,
+ bool response_expected,
+ bool header_present)
+{
+ const struct gen_device_info *devinfo = p->devinfo;
+
+ assert(devinfo->gen >= 9);
+ assert(brw_get_default_access_mode(p) == BRW_ALIGN_1);
+
+ const unsigned sfid = HSW_SFID_DATAPORT_DATA_CACHE_1;
+ const unsigned response_length = brw_surface_payload_size(
+ p, response_expected, true, true);
+ const unsigned desc =
+ brw_message_desc(devinfo, msg_length, response_length, header_present) |
+ brw_dp_untyped_atomic_float_desc(p, atomic_op, response_expected);
+
+ brw_send_indirect_surface_message(p, sfid,
+ brw_writemask(dst, WRITEMASK_XYZW),
+ payload, surface, desc);
+}
+
+static uint32_t
brw_dp_untyped_surface_read_desc(struct brw_codegen *p,
unsigned num_channels)
{