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-rw-r--r--src/gallium/drivers/freedreno/a6xx/fd6_emit.c22
-rw-r--r--src/gallium/drivers/freedreno/a6xx/fd6_emit.h18
-rw-r--r--src/gallium/drivers/freedreno/a6xx/fd6_program.c16
3 files changed, 21 insertions, 35 deletions
diff --git a/src/gallium/drivers/freedreno/a6xx/fd6_emit.c b/src/gallium/drivers/freedreno/a6xx/fd6_emit.c
index d17be0949a6..846cd4f141e 100644
--- a/src/gallium/drivers/freedreno/a6xx/fd6_emit.c
+++ b/src/gallium/drivers/freedreno/a6xx/fd6_emit.c
@@ -45,24 +45,6 @@
#include "fd6_format.h"
#include "fd6_zsa.h"
-static uint32_t
-shader_t_to_opcode(gl_shader_stage type)
-{
- switch (type) {
- case MESA_SHADER_VERTEX:
- case MESA_SHADER_TESS_CTRL:
- case MESA_SHADER_TESS_EVAL:
- case MESA_SHADER_GEOMETRY:
- return CP_LOAD_STATE6_GEOM;
- case MESA_SHADER_FRAGMENT:
- case MESA_SHADER_COMPUTE:
- case MESA_SHADER_KERNEL:
- return CP_LOAD_STATE6_FRAG;
- default:
- unreachable("bad shader type");
- }
-}
-
/* regid: base const register
* prsc or dwords: buffer containing constant values
* sizedwords: size of const value buffer
@@ -87,7 +69,7 @@ fd6_emit_const(struct fd_ringbuffer *ring, gl_shader_stage type,
align_sz = align(sz, 4);
- OUT_PKT7(ring, shader_t_to_opcode(type), 3 + align_sz);
+ OUT_PKT7(ring, fd6_stage2opcode(type), 3 + align_sz);
OUT_RING(ring, CP_LOAD_STATE6_0_DST_OFF(regid/4) |
CP_LOAD_STATE6_0_STATE_TYPE(ST6_CONSTANTS) |
CP_LOAD_STATE6_0_STATE_SRC(src) |
@@ -121,7 +103,7 @@ fd6_emit_const_bo(struct fd_ringbuffer *ring, gl_shader_stage type, boolean writ
debug_assert((regid % 4) == 0);
- OUT_PKT7(ring, shader_t_to_opcode(type), 3 + (2 * anum));
+ OUT_PKT7(ring, fd6_stage2opcode(type), 3 + (2 * anum));
OUT_RING(ring, CP_LOAD_STATE6_0_DST_OFF(regid/4) |
CP_LOAD_STATE6_0_STATE_TYPE(ST6_CONSTANTS)|
CP_LOAD_STATE6_0_STATE_SRC(SS6_DIRECT) |
diff --git a/src/gallium/drivers/freedreno/a6xx/fd6_emit.h b/src/gallium/drivers/freedreno/a6xx/fd6_emit.h
index 5c86b992740..691467a0786 100644
--- a/src/gallium/drivers/freedreno/a6xx/fd6_emit.h
+++ b/src/gallium/drivers/freedreno/a6xx/fd6_emit.h
@@ -186,6 +186,24 @@ fd6_emit_lrz_flush(struct fd_ringbuffer *ring)
OUT_RING(ring, LRZ_FLUSH);
}
+static inline uint32_t
+fd6_stage2opcode(gl_shader_stage type)
+{
+ switch (type) {
+ case MESA_SHADER_VERTEX:
+ case MESA_SHADER_TESS_CTRL:
+ case MESA_SHADER_TESS_EVAL:
+ case MESA_SHADER_GEOMETRY:
+ return CP_LOAD_STATE6_GEOM;
+ case MESA_SHADER_FRAGMENT:
+ case MESA_SHADER_COMPUTE:
+ case MESA_SHADER_KERNEL:
+ return CP_LOAD_STATE6_FRAG;
+ default:
+ unreachable("bad shader type");
+ }
+}
+
static inline enum a6xx_state_block
fd6_stage2shadersb(gl_shader_stage type)
{
diff --git a/src/gallium/drivers/freedreno/a6xx/fd6_program.c b/src/gallium/drivers/freedreno/a6xx/fd6_program.c
index 2c982cc1afc..dd43646c436 100644
--- a/src/gallium/drivers/freedreno/a6xx/fd6_program.c
+++ b/src/gallium/drivers/freedreno/a6xx/fd6_program.c
@@ -87,7 +87,6 @@ fd6_emit_shader(struct fd_ringbuffer *ring, const struct ir3_shader_variant *so)
enum a6xx_state_block sb = fd6_stage2shadersb(so->type);
enum a6xx_state_src src;
uint32_t i, sz, *bin;
- unsigned opcode;
if (fd_mesa_debug & FD_DBG_DIRECT) {
sz = si->sizedwords;
@@ -99,20 +98,7 @@ fd6_emit_shader(struct fd_ringbuffer *ring, const struct ir3_shader_variant *so)
bin = NULL;
}
- switch (so->type) {
- case MESA_SHADER_VERTEX:
- opcode = CP_LOAD_STATE6_GEOM;
- break;
- case MESA_SHADER_FRAGMENT:
- case MESA_SHADER_COMPUTE:
- case MESA_SHADER_KERNEL:
- opcode = CP_LOAD_STATE6_FRAG;
- break;
- default:
- unreachable("bad shader type");
- }
-
- OUT_PKT7(ring, opcode, 3 + sz);
+ OUT_PKT7(ring, fd6_stage2opcode(so->type), 3 + sz);
OUT_RING(ring, CP_LOAD_STATE6_0_DST_OFF(0) |
CP_LOAD_STATE6_0_STATE_TYPE(ST6_SHADER) |
CP_LOAD_STATE6_0_STATE_SRC(src) |