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-rw-r--r--src/gallium/winsys/r600/drm/r600_state.c133
-rw-r--r--src/gallium/winsys/r600/drm/r600_states.h144
-rw-r--r--src/gallium/winsys/r600/drm/radeon.c44
-rw-r--r--src/gallium/winsys/r600/drm/radeon_ctx.c6
-rw-r--r--src/gallium/winsys/r600/drm/radeon_draw.c11
-rw-r--r--src/gallium/winsys/r600/drm/radeon_priv.h32
-rw-r--r--src/gallium/winsys/r600/drm/radeon_state.c58
7 files changed, 210 insertions, 218 deletions
diff --git a/src/gallium/winsys/r600/drm/r600_state.c b/src/gallium/winsys/r600/drm/r600_state.c
index 9b7c11bdc06..e3d0116a2d1 100644
--- a/src/gallium/winsys/r600/drm/r600_state.c
+++ b/src/gallium/winsys/r600/drm/r600_state.c
@@ -30,6 +30,8 @@
#include "radeon_priv.h"
#include "r600d.h"
+#include "util/u_memory.h"
+
static int r600_state_pm4_resource(struct radeon_state *state);
static int r600_state_pm4_cb0(struct radeon_state *state);
static int r600_state_pm4_vgt(struct radeon_state *state);
@@ -46,18 +48,61 @@ static int r700_state_pm4_db(struct radeon_state *state);
#include "r600_states.h"
+
+#define SUB_NONE(param) { { 0, R600_names_##param, (sizeof(R600_names_##param)/sizeof(struct radeon_register)) } }
+#define SUB_PS(param) { R600_SHADER_PS, R600_names_##param, (sizeof(R600_names_##param)/sizeof(struct radeon_register)) }
+#define SUB_VS(param) { R600_SHADER_VS, R600_names_##param, (sizeof(R600_names_##param)/sizeof(struct radeon_register)) }
+#define SUB_GS(param) { R600_SHADER_GS, R600_names_##param, (sizeof(R600_names_##param)/sizeof(struct radeon_register)) }
+#define SUB_FS(param) { R600_SHADER_FS, R600_names_##param, (sizeof(R600_names_##param)/sizeof(struct radeon_register)) }
+
+/* some of these are overriden at runtime for R700 */
+struct radeon_stype_info r600_stypes[] = {
+ { R600_STATE_CONFIG, 1, 0, r600_state_pm4_config, SUB_NONE(CONFIG), },
+ { R600_STATE_CB_CNTL, 1, 0, r600_state_pm4_generic, SUB_NONE(CB_CNTL) },
+ { R600_STATE_RASTERIZER, 1, 0, r600_state_pm4_generic, SUB_NONE(RASTERIZER) },
+ { R600_STATE_VIEWPORT, 1, 0, r600_state_pm4_generic, SUB_NONE(VIEWPORT) },
+ { R600_STATE_SCISSOR, 1, 0, r600_state_pm4_generic, SUB_NONE(SCISSOR) },
+ { R600_STATE_BLEND, 1, 0, r600_state_pm4_generic, SUB_NONE(BLEND), },
+ { R600_STATE_DSA, 1, 0, r600_state_pm4_generic, SUB_NONE(DSA), },
+ { R600_STATE_SHADER, 1, 0, r600_state_pm4_shader, { SUB_PS(PS_SHADER), SUB_VS(VS_SHADER) } },
+ { R600_STATE_CONSTANT, 256, 0x10, r600_state_pm4_generic, { SUB_PS(PS_CONSTANT), SUB_VS(VS_CONSTANT) } },
+ { R600_STATE_RESOURCE, 160, 0x1c, r600_state_pm4_resource, { SUB_PS(PS_RESOURCE), SUB_VS(VS_RESOURCE), SUB_GS(GS_RESOURCE), SUB_FS(FS_RESOURCE)} },
+ { R600_STATE_SAMPLER, 18, 0xc, r600_state_pm4_generic, { SUB_PS(PS_SAMPLER), SUB_VS(VS_SAMPLER), SUB_GS(GS_SAMPLER) } },
+ { R600_STATE_SAMPLER_BORDER, 18, 0x10, r600_state_pm4_generic, { SUB_PS(PS_SAMPLER_BORDER), SUB_VS(VS_SAMPLER_BORDER), SUB_GS(GS_SAMPLER_BORDER) } },
+ { R600_STATE_CB0, 1, 0, r600_state_pm4_cb0, SUB_NONE(CB0) },
+ { R600_STATE_CB1, 1, 0, r600_state_pm4_cb0, SUB_NONE(CB1) },
+ { R600_STATE_CB2, 1, 0, r600_state_pm4_cb0, SUB_NONE(CB2) },
+ { R600_STATE_CB3, 1, 0, r600_state_pm4_cb0, SUB_NONE(CB3) },
+ { R600_STATE_CB4, 1, 0, r600_state_pm4_cb0, SUB_NONE(CB4) },
+ { R600_STATE_CB5, 1, 0, r600_state_pm4_cb0, SUB_NONE(CB5) },
+ { R600_STATE_CB6, 1, 0, r600_state_pm4_cb0, SUB_NONE(CB6) },
+ { R600_STATE_CB7, 1, 0, r600_state_pm4_cb0, SUB_NONE(CB7) },
+ { R600_STATE_QUERY_BEGIN, 1, 0, r600_state_pm4_query_begin, SUB_NONE(VGT_EVENT) },
+ { R600_STATE_QUERY_END, 1, 0, r600_state_pm4_query_end, SUB_NONE(VGT_EVENT) },
+ { R600_STATE_DB, 1, 0, r600_state_pm4_db, SUB_NONE(DB) },
+ { R600_STATE_CLIP, 6, 0, r600_state_pm4_generic, SUB_NONE(UCP) },
+ { R600_STATE_VGT, 1, 0, r600_state_pm4_vgt, SUB_NONE(VGT) },
+ { R600_STATE_DRAW, 1, 0, r600_state_pm4_draw, SUB_NONE(DRAW) },
+};
+#define STYPES_SIZE Elements(r600_stypes)
+
+static const struct radeon_register *get_regs(struct radeon_state *state)
+{
+ return state->stype->reginfo[state->shader_index].regs;
+}
+
/*
* r600/r700 state functions
*/
static int r600_state_pm4_bytecode(struct radeon_state *state, unsigned offset, unsigned id, unsigned nreg)
{
- const struct radeon_register *regs = state->radeon->type[state->type].regs;
+ const struct radeon_register *regs = get_regs(state);
unsigned i;
int r;
if (!offset) {
fprintf(stderr, "%s invalid register for state %d %d\n",
- __func__, state->type, id);
+ __func__, state->stype->stype, id);
return -EINVAL;
}
if (offset >= R600_CONFIG_REG_OFFSET && offset < R600_CONFIG_REG_END) {
@@ -116,19 +161,18 @@ static int r600_state_pm4_bytecode(struct radeon_state *state, unsigned offset,
static int r600_state_pm4_generic(struct radeon_state *state)
{
- struct radeon *radeon = state->radeon;
- unsigned i, offset, nreg, type, coffset, loffset, soffset;
+ const struct radeon_register *regs = get_regs(state);
+ unsigned i, offset, nreg, coffset, loffset, soffset;
unsigned start;
int r;
if (!state->nstates)
return 0;
- type = state->type;
- soffset = (state->id - radeon->type[type].id) * radeon->type[type].stride;
- offset = loffset = radeon->type[type].regs[0].offset + soffset;
+ soffset = state->id * state->stype->stride;
+ offset = loffset = regs[0].offset + soffset;
start = 0;
for (i = 1, nreg = 1; i < state->nstates; i++) {
- coffset = radeon->type[type].regs[i].offset + soffset;
+ coffset = regs[i].offset + soffset;
if (coffset == (loffset + 4)) {
nreg++;
loffset = coffset;
@@ -358,8 +402,9 @@ static int r600_state_pm4_resource(struct radeon_state *state)
{
u32 flags, type, nbo, offset, soffset;
int r;
+ const struct radeon_register *regs = get_regs(state);
- soffset = (state->id - state->radeon->type[state->type].id) * state->radeon->type[state->type].stride;
+ soffset = state->id * state->stype->stride;
type = G_038018_TYPE(state->states[6]);
switch (type) {
case 2:
@@ -378,7 +423,7 @@ static int r600_state_pm4_resource(struct radeon_state *state)
return -EINVAL;
}
r600_state_pm4_with_flush(state, flags);
- offset = state->radeon->type[state->type].regs[0].offset + soffset;
+ offset = regs[0].offset + soffset;
state->pm4[state->cpm4++] = PKT3(PKT3_SET_RESOURCE, 7);
state->pm4[state->cpm4++] = (offset - R_038000_SQ_TEX_RESOURCE_WORD0_0) >> 2;
state->pm4[state->cpm4++] = state->states[0];
@@ -403,33 +448,63 @@ static int r600_state_pm4_resource(struct radeon_state *state)
return 0;
}
-int r600_init(struct radeon *radeon)
+
+static void r600_modify_type_array(struct radeon *radeon)
{
+ int i;
switch (radeon->family) {
- case CHIP_R600:
- case CHIP_RV610:
- case CHIP_RV630:
- case CHIP_RV670:
- case CHIP_RV620:
- case CHIP_RV635:
- case CHIP_RS780:
- case CHIP_RS880:
- radeon->ntype = R600_NTYPE;
- radeon->nstate = R600_NSTATE;
- radeon->type = R600_types;
- break;
case CHIP_RV770:
case CHIP_RV730:
case CHIP_RV710:
case CHIP_RV740:
- radeon->ntype = R600_NTYPE;
- radeon->nstate = R600_NSTATE;
- radeon->type = R700_types;
break;
default:
- fprintf(stderr, "%s unknown or unsupported chipset 0x%04X\n",
- __func__, radeon->device);
- return -EINVAL;
+ return;
+ }
+
+ /* r700 needs some mods */
+ for (i = 0; i < radeon->nstype; i++) {
+ struct radeon_stype_info *info = &radeon->stype[i];
+
+ switch(info->stype) {
+ case R600_STATE_CONFIG:
+ info->pm4 = r700_state_pm4_config;
+ break;
+ case R600_STATE_CB0:
+ info->pm4 = r700_state_pm4_cb0;
+ break;
+ case R600_STATE_DB:
+ info->pm4 = r700_state_pm4_db;
+ };
}
+}
+
+static void r600_build_types_array(struct radeon *radeon)
+{
+ int i, j;
+ int id = 0;
+
+ for (i = 0; i < STYPES_SIZE; i++) {
+ r600_stypes[i].base_id = id;
+ r600_stypes[i].npm4 = 128;
+ if (r600_stypes[i].reginfo[0].shader_type == 0) {
+ id += r600_stypes[i].num;
+ } else {
+ for (j = 0; j < R600_SHADER_MAX; j++) {
+ if (r600_stypes[i].reginfo[j].shader_type)
+ id += r600_stypes[i].num;
+ }
+ }
+ }
+ radeon->nstate = id;
+ radeon->stype = r600_stypes;
+ radeon->nstype = STYPES_SIZE;
+
+ r600_modify_type_array(radeon);
+}
+
+int r600_init(struct radeon *radeon)
+{
+ r600_build_types_array(radeon);
return 0;
}
diff --git a/src/gallium/winsys/r600/drm/r600_states.h b/src/gallium/winsys/r600/drm/r600_states.h
index b5365e4275a..51b69b92206 100644
--- a/src/gallium/winsys/r600/drm/r600_states.h
+++ b/src/gallium/winsys/r600/drm/r600_states.h
@@ -17,7 +17,7 @@
#ifndef R600_STATES_H
#define R600_STATES_H
-static const struct radeon_register R600_CONFIG_names[] = {
+static const struct radeon_register R600_names_CONFIG[] = {
{0x00008C00, 0, 0, "SQ_CONFIG"},
{0x00008C04, 0, 0, "SQ_GPR_RESOURCE_MGMT_1"},
{0x00008C08, 0, 0, "SQ_GPR_RESOURCE_MGMT_2"},
@@ -61,7 +61,7 @@ static const struct radeon_register R600_CONFIG_names[] = {
{0x00028B20, 0, 0, "VGT_STRMOUT_BUFFER_EN"},
};
-static const struct radeon_register R600_CB_CNTL_names[] = {
+static const struct radeon_register R600_names_CB_CNTL[] = {
{0x00028120, 0, 0, "CB_CLEAR_RED"},
{0x00028124, 0, 0, "CB_CLEAR_GREEN"},
{0x00028128, 0, 0, "CB_CLEAR_BLUE"},
@@ -82,7 +82,7 @@ static const struct radeon_register R600_CB_CNTL_names[] = {
{0x00028C48, 0, 0, "PA_SC_AA_MASK"},
};
-static const struct radeon_register R600_RASTERIZER_names[] = {
+static const struct radeon_register R600_names_RASTERIZER[] = {
{0x000286D4, 0, 0, "SPI_INTERP_CONTROL_0"},
{0x00028810, 0, 0, "PA_CL_CLIP_CNTL"},
{0x00028814, 0, 0, "PA_SU_SC_MODE_CNTL"},
@@ -106,7 +106,7 @@ static const struct radeon_register R600_RASTERIZER_names[] = {
{0x00028E0C, 0, 0, "PA_SU_POLY_OFFSET_BACK_OFFSET"},
};
-static const struct radeon_register R600_VIEWPORT_names[] = {
+static const struct radeon_register R600_names_VIEWPORT[] = {
{0x000282D0, 0, 0, "PA_SC_VPORT_ZMIN_0"},
{0x000282D4, 0, 0, "PA_SC_VPORT_ZMAX_0"},
{0x0002843C, 0, 0, "PA_CL_VPORT_XSCALE_0"},
@@ -118,7 +118,7 @@ static const struct radeon_register R600_VIEWPORT_names[] = {
{0x00028818, 0, 0, "PA_CL_VTE_CNTL"},
};
-static const struct radeon_register R600_SCISSOR_names[] = {
+static const struct radeon_register R600_names_SCISSOR[] = {
{0x00028030, 0, 0, "PA_SC_SCREEN_SCISSOR_TL"},
{0x00028034, 0, 0, "PA_SC_SCREEN_SCISSOR_BR"},
{0x00028200, 0, 0, "PA_SC_WINDOW_OFFSET"},
@@ -140,7 +140,7 @@ static const struct radeon_register R600_SCISSOR_names[] = {
{0x00028254, 0, 0, "PA_SC_VPORT_SCISSOR_0_BR"},
};
-static const struct radeon_register R600_BLEND_names[] = {
+static const struct radeon_register R600_names_BLEND[] = {
{0x00028414, 0, 0, "CB_BLEND_RED"},
{0x00028418, 0, 0, "CB_BLEND_GREEN"},
{0x0002841C, 0, 0, "CB_BLEND_BLUE"},
@@ -156,7 +156,7 @@ static const struct radeon_register R600_BLEND_names[] = {
{0x00028804, 0, 0, "CB_BLEND_CONTROL"},
};
-static const struct radeon_register R600_DSA_names[] = {
+static const struct radeon_register R600_names_DSA[] = {
{0x00028028, 0, 0, "DB_STENCIL_CLEAR"},
{0x0002802C, 0, 0, "DB_DEPTH_CLEAR"},
{0x00028410, 0, 0, "SX_ALPHA_TEST_CONTROL"},
@@ -175,7 +175,7 @@ static const struct radeon_register R600_DSA_names[] = {
{0x00028D44, 0, 0, "DB_ALPHA_TO_MASK"},
};
-static const struct radeon_register R600_VS_SHADER_names[] = {
+static const struct radeon_register R600_names_VS_SHADER[] = {
{0x00028380, 0, 0, "SQ_VTX_SEMANTIC_0"},
{0x00028384, 0, 0, "SQ_VTX_SEMANTIC_1"},
{0x00028388, 0, 0, "SQ_VTX_SEMANTIC_2"},
@@ -227,7 +227,7 @@ static const struct radeon_register R600_VS_SHADER_names[] = {
{0x000288DC, 0, 0, "SQ_PGM_CF_OFFSET_FS"},
};
-static const struct radeon_register R600_PS_SHADER_names[] = {
+static const struct radeon_register R600_names_PS_SHADER[] = {
{0x00028644, 0, 0, "SPI_PS_INPUT_CNTL_0"},
{0x00028648, 0, 0, "SPI_PS_INPUT_CNTL_1"},
{0x0002864C, 0, 0, "SPI_PS_INPUT_CNTL_2"},
@@ -269,28 +269,28 @@ static const struct radeon_register R600_PS_SHADER_names[] = {
{0x000288CC, 0, 0, "SQ_PGM_CF_OFFSET_PS"},
};
-static const struct radeon_register R600_PS_CONSTANT_names[] = {
+static const struct radeon_register R600_names_PS_CONSTANT[] = {
{0x00030000, 0, 0, "SQ_ALU_CONSTANT0_0"},
{0x00030004, 0, 0, "SQ_ALU_CONSTANT1_0"},
{0x00030008, 0, 0, "SQ_ALU_CONSTANT2_0"},
{0x0003000C, 0, 0, "SQ_ALU_CONSTANT3_0"},
};
-static const struct radeon_register R600_VS_CONSTANT_names[] = {
+static const struct radeon_register R600_names_VS_CONSTANT[] = {
{0x00031000, 0, 0, "SQ_ALU_CONSTANT0_256"},
{0x00031004, 0, 0, "SQ_ALU_CONSTANT1_256"},
{0x00031008, 0, 0, "SQ_ALU_CONSTANT2_256"},
{0x0003100C, 0, 0, "SQ_ALU_CONSTANT3_256"},
};
-static const struct radeon_register R600_UCP_names[] = {
+static const struct radeon_register R600_names_UCP[] = {
{0x00028e20, 0, 0, "PA_CL_UCP0_X"},
{0x00028e24, 0, 0, "PA_CL_UCP0_Y"},
{0x00028e28, 0, 0, "PA_CL_UCP0_Z"},
{0x00028e2c, 0, 0, "PA_CL_UCP0_W"},
};
-static const struct radeon_register R600_PS_RESOURCE_names[] = {
+static const struct radeon_register R600_names_PS_RESOURCE[] = {
{0x00038000, 0, 0, "RESOURCE0_WORD0"},
{0x00038004, 0, 0, "RESOURCE0_WORD1"},
{0x00038008, 0, 0, "RESOURCE0_WORD2"},
@@ -300,7 +300,7 @@ static const struct radeon_register R600_PS_RESOURCE_names[] = {
{0x00038018, 0, 0, "RESOURCE0_WORD6"},
};
-static const struct radeon_register R600_VS_RESOURCE_names[] = {
+static const struct radeon_register R600_names_VS_RESOURCE[] = {
{0x00039180, 0, 0, "RESOURCE160_WORD0"},
{0x00039184, 0, 0, "RESOURCE160_WORD1"},
{0x00039188, 0, 0, "RESOURCE160_WORD2"},
@@ -310,7 +310,7 @@ static const struct radeon_register R600_VS_RESOURCE_names[] = {
{0x00039198, 0, 0, "RESOURCE160_WORD6"},
};
-static const struct radeon_register R600_FS_RESOURCE_names[] = {
+static const struct radeon_register R600_names_FS_RESOURCE[] = {
{0x0003A300, 0, 0, "RESOURCE320_WORD0"},
{0x0003A304, 0, 0, "RESOURCE320_WORD1"},
{0x0003A308, 0, 0, "RESOURCE320_WORD2"},
@@ -320,7 +320,7 @@ static const struct radeon_register R600_FS_RESOURCE_names[] = {
{0x0003A318, 0, 0, "RESOURCE320_WORD6"},
};
-static const struct radeon_register R600_GS_RESOURCE_names[] = {
+static const struct radeon_register R600_names_GS_RESOURCE[] = {
{0x0003A4C0, 0, 0, "RESOURCE336_WORD0"},
{0x0003A4C4, 0, 0, "RESOURCE336_WORD1"},
{0x0003A4C8, 0, 0, "RESOURCE336_WORD2"},
@@ -330,46 +330,46 @@ static const struct radeon_register R600_GS_RESOURCE_names[] = {
{0x0003A4D8, 0, 0, "RESOURCE336_WORD6"},
};
-static const struct radeon_register R600_PS_SAMPLER_names[] = {
+static const struct radeon_register R600_names_PS_SAMPLER[] = {
{0x0003C000, 0, 0, "SQ_TEX_SAMPLER_WORD0_0"},
{0x0003C004, 0, 0, "SQ_TEX_SAMPLER_WORD1_0"},
{0x0003C008, 0, 0, "SQ_TEX_SAMPLER_WORD2_0"},
};
-static const struct radeon_register R600_VS_SAMPLER_names[] = {
+static const struct radeon_register R600_names_VS_SAMPLER[] = {
{0x0003C0D8, 0, 0, "SQ_TEX_SAMPLER_WORD0_18"},
{0x0003C0DC, 0, 0, "SQ_TEX_SAMPLER_WORD1_18"},
{0x0003C0E0, 0, 0, "SQ_TEX_SAMPLER_WORD2_18"},
};
-static const struct radeon_register R600_GS_SAMPLER_names[] = {
+static const struct radeon_register R600_names_GS_SAMPLER[] = {
{0x0003C1B0, 0, 0, "SQ_TEX_SAMPLER_WORD0_36"},
{0x0003C1B4, 0, 0, "SQ_TEX_SAMPLER_WORD1_36"},
{0x0003C1B8, 0, 0, "SQ_TEX_SAMPLER_WORD2_36"},
};
-static const struct radeon_register R600_PS_SAMPLER_BORDER_names[] = {
+static const struct radeon_register R600_names_PS_SAMPLER_BORDER[] = {
{0x0000A400, 0, 0, "TD_PS_SAMPLER0_BORDER_RED"},
{0x0000A404, 0, 0, "TD_PS_SAMPLER0_BORDER_GREEN"},
{0x0000A408, 0, 0, "TD_PS_SAMPLER0_BORDER_BLUE"},
{0x0000A40C, 0, 0, "TD_PS_SAMPLER0_BORDER_ALPHA"},
};
-static const struct radeon_register R600_VS_SAMPLER_BORDER_names[] = {
+static const struct radeon_register R600_names_VS_SAMPLER_BORDER[] = {
{0x0000A600, 0, 0, "TD_VS_SAMPLER0_BORDER_RED"},
{0x0000A604, 0, 0, "TD_VS_SAMPLER0_BORDER_GREEN"},
{0x0000A608, 0, 0, "TD_VS_SAMPLER0_BORDER_BLUE"},
{0x0000A60C, 0, 0, "TD_VS_SAMPLER0_BORDER_ALPHA"},
};
-static const struct radeon_register R600_GS_SAMPLER_BORDER_names[] = {
+static const struct radeon_register R600_names_GS_SAMPLER_BORDER[] = {
{0x0000A800, 0, 0, "TD_GS_SAMPLER0_BORDER_RED"},
{0x0000A804, 0, 0, "TD_GS_SAMPLER0_BORDER_GREEN"},
{0x0000A808, 0, 0, "TD_GS_SAMPLER0_BORDER_BLUE"},
{0x0000A80C, 0, 0, "TD_GS_SAMPLER0_BORDER_ALPHA"},
};
-static const struct radeon_register R600_CB0_names[] = {
+static const struct radeon_register R600_names_CB0[] = {
{0x00028040, 1, 0, "CB_COLOR0_BASE"},
{0x000280A0, 0, 0, "CB_COLOR0_INFO"},
{0x00028060, 0, 0, "CB_COLOR0_SIZE"},
@@ -379,7 +379,7 @@ static const struct radeon_register R600_CB0_names[] = {
{0x00028100, 0, 0, "CB_COLOR0_MASK"},
};
-static const struct radeon_register R600_CB1_names[] = {
+static const struct radeon_register R600_names_CB1[] = {
{0x00028044, 1, 0, "CB_COLOR1_BASE"},
{0x000280A4, 0, 0, "CB_COLOR1_INFO"},
{0x00028064, 0, 0, "CB_COLOR1_SIZE"},
@@ -389,7 +389,7 @@ static const struct radeon_register R600_CB1_names[] = {
{0x00028104, 0, 0, "CB_COLOR1_MASK"},
};
-static const struct radeon_register R600_CB2_names[] = {
+static const struct radeon_register R600_names_CB2[] = {
{0x00028048, 1, 0, "CB_COLOR2_BASE"},
{0x000280A8, 0, 0, "CB_COLOR2_INFO"},
{0x00028068, 0, 0, "CB_COLOR2_SIZE"},
@@ -399,7 +399,7 @@ static const struct radeon_register R600_CB2_names[] = {
{0x00028108, 0, 0, "CB_COLOR2_MASK"},
};
-static const struct radeon_register R600_CB3_names[] = {
+static const struct radeon_register R600_names_CB3[] = {
{0x0002804C, 1, 0, "CB_COLOR3_BASE"},
{0x000280AC, 0, 0, "CB_COLOR3_INFO"},
{0x0002806C, 0, 0, "CB_COLOR3_SIZE"},
@@ -409,7 +409,7 @@ static const struct radeon_register R600_CB3_names[] = {
{0x0002810C, 0, 0, "CB_COLOR3_MASK"},
};
-static const struct radeon_register R600_CB4_names[] = {
+static const struct radeon_register R600_names_CB4[] = {
{0x00028050, 1, 0, "CB_COLOR4_BASE"},
{0x000280B0, 0, 0, "CB_COLOR4_INFO"},
{0x00028070, 0, 0, "CB_COLOR4_SIZE"},
@@ -419,7 +419,7 @@ static const struct radeon_register R600_CB4_names[] = {
{0x00028110, 0, 0, "CB_COLOR4_MASK"},
};
-static const struct radeon_register R600_CB5_names[] = {
+static const struct radeon_register R600_names_CB5[] = {
{0x00028054, 1, 0, "CB_COLOR5_BASE"},
{0x000280B4, 0, 0, "CB_COLOR5_INFO"},
{0x00028074, 0, 0, "CB_COLOR5_SIZE"},
@@ -429,7 +429,7 @@ static const struct radeon_register R600_CB5_names[] = {
{0x00028114, 0, 0, "CB_COLOR5_MASK"},
};
-static const struct radeon_register R600_CB6_names[] = {
+static const struct radeon_register R600_names_CB6[] = {
{0x00028058, 1, 0, "CB_COLOR6_BASE"},
{0x000280B8, 0, 0, "CB_COLOR6_INFO"},
{0x00028078, 0, 0, "CB_COLOR6_SIZE"},
@@ -439,7 +439,7 @@ static const struct radeon_register R600_CB6_names[] = {
{0x00028118, 0, 0, "CB_COLOR6_MASK"},
};
-static const struct radeon_register R600_CB7_names[] = {
+static const struct radeon_register R600_names_CB7[] = {
{0x0002805C, 1, 0, "CB_COLOR7_BASE"},
{0x000280BC, 0, 0, "CB_COLOR7_INFO"},
{0x0002807C, 0, 0, "CB_COLOR7_SIZE"},
@@ -449,7 +449,7 @@ static const struct radeon_register R600_CB7_names[] = {
{0x0002811C, 0, 0, "CB_COLOR7_MASK"},
};
-static const struct radeon_register R600_DB_names[] = {
+static const struct radeon_register R600_names_DB[] = {
{0x0002800C, 1, 0, "DB_DEPTH_BASE"},
{0x00028000, 0, 0, "DB_DEPTH_SIZE"},
{0x00028004, 0, 0, "DB_DEPTH_VIEW"},
@@ -458,7 +458,7 @@ static const struct radeon_register R600_DB_names[] = {
{0x00028D34, 0, 0, "DB_PREFETCH_LIMIT"},
};
-static const struct radeon_register R600_VGT_names[] = {
+static const struct radeon_register R600_names_VGT[] = {
{0x00008958, 0, 0, "VGT_PRIMITIVE_TYPE"},
{0x00028400, 0, 0, "VGT_MAX_VTX_INDX"},
{0x00028404, 0, 0, "VGT_MIN_VTX_INDX"},
@@ -472,91 +472,15 @@ static const struct radeon_register R600_VGT_names[] = {
{0x00028AA4, 0, 0, "VGT_INSTANCE_STEP_RATE_1"},
};
-static const struct radeon_register R600_DRAW_names[] = {
+static const struct radeon_register R600_names_DRAW[] = {
{0x00008970, 0, 0, "VGT_NUM_INDICES"},
{0x000287E4, 0, 0, "VGT_DMA_BASE_HI"},
{0x000287E8, 1, 0, "VGT_DMA_BASE"},
{0x000287F0, 0, 0, "VGT_DRAW_INITIATOR"},
};
-static const struct radeon_register R600_VGT_EVENT_names[] = {
+static const struct radeon_register R600_names_VGT_EVENT[] = {
{0x00028A90, 1, 0, "VGT_EVENT_INITIATOR"},
};
-static struct radeon_type R600_types[] = {
- { 128, 0, 0x00000000, 0x00000000, 0x0000, 0, "R600_CONFIG", 41, r600_state_pm4_config, R600_CONFIG_names},
- { 128, 1, 0x00000000, 0x00000000, 0x0000, 0, "R600_CB_CNTL", 18, r600_state_pm4_generic, R600_CB_CNTL_names},
- { 128, 2, 0x00000000, 0x00000000, 0x0000, 0, "R600_RASTERIZER", 21, r600_state_pm4_generic, R600_RASTERIZER_names},
- { 128, 3, 0x00000000, 0x00000000, 0x0000, 0, "R600_VIEWPORT", 9, r600_state_pm4_generic, R600_VIEWPORT_names},
- { 128, 4, 0x00000000, 0x00000000, 0x0000, 0, "R600_SCISSOR", 19, r600_state_pm4_generic, R600_SCISSOR_names},
- { 128, 5, 0x00000000, 0x00000000, 0x0000, 0, "R600_BLEND", 13, r600_state_pm4_generic, R600_BLEND_names},
- { 128, 6, 0x00000000, 0x00000000, 0x0000, 0, "R600_DSA", 16, r600_state_pm4_generic, R600_DSA_names},
- { 128, 7, 0x00000000, 0x00000000, 0x0000, 0, "R600_VS_SHADER", 49, r600_state_pm4_shader, R600_VS_SHADER_names},
- { 128, 8, 0x00000000, 0x00000000, 0x0000, 0, "R600_PS_SHADER", 39, r600_state_pm4_shader, R600_PS_SHADER_names},
- { 128, 9, 0x00030000, 0x00031000, 0x0010, 0, "R600_PS_CONSTANT", 4, r600_state_pm4_generic, R600_PS_CONSTANT_names},
- { 128, 265, 0x00031000, 0x00032000, 0x0010, 0, "R600_VS_CONSTANT", 4, r600_state_pm4_generic, R600_VS_CONSTANT_names},
- { 128, 521, 0x00038000, 0x00039180, 0x001C, 0, "R600_PS_RESOURCE", 7, r600_state_pm4_resource, R600_PS_RESOURCE_names},
- { 128, 681, 0x00039180, 0x0003A300, 0x001C, 0, "R600_VS_RESOURCE", 7, r600_state_pm4_resource, R600_VS_RESOURCE_names},
- { 128, 841, 0x00039180, 0x0003A300, 0x001C, 0, "R600_FS_RESOURCE", 7, r600_state_pm4_resource, R600_FS_RESOURCE_names},
- { 128, 1001, 0x00039180, 0x0003A300, 0x001C, 0, "R600_GS_RESOURCE", 7, r600_state_pm4_resource, R600_GS_RESOURCE_names},
- { 128, 1161, 0x0003C000, 0x0003C0D8, 0x000C, 0, "R600_PS_SAMPLER", 3, r600_state_pm4_generic, R600_PS_SAMPLER_names},
- { 128, 1179, 0x0003C0D8, 0x0003C1B0, 0x000C, 0, "R600_VS_SAMPLER", 3, r600_state_pm4_generic, R600_VS_SAMPLER_names},
- { 128, 1197, 0x0003C1B0, 0x0003C288, 0x000C, 0, "R600_GS_SAMPLER", 3, r600_state_pm4_generic, R600_GS_SAMPLER_names},
- { 128, 1215, 0x0000A400, 0x0000A520, 0x0010, 0, "R600_PS_SAMPLER_BORDER", 4, r600_state_pm4_generic, R600_PS_SAMPLER_BORDER_names},
- { 128, 1233, 0x0000A600, 0x0000A720, 0x0010, 0, "R600_VS_SAMPLER_BORDER", 4, r600_state_pm4_generic, R600_VS_SAMPLER_BORDER_names},
- { 128, 1251, 0x0000A800, 0x0000A920, 0x0010, 0, "R600_GS_SAMPLER_BORDER", 4, r600_state_pm4_generic, R600_GS_SAMPLER_BORDER_names},
- { 128, 1269, 0x00000000, 0x00000000, 0x0000, 0, "R600_CB0", 7, r600_state_pm4_cb0, R600_CB0_names},
- { 128, 1270, 0x00000000, 0x00000000, 0x0000, 0, "R600_CB1", 7, r600_state_pm4_cb0, R600_CB1_names},
- { 128, 1271, 0x00000000, 0x00000000, 0x0000, 0, "R600_CB2", 7, r600_state_pm4_cb0, R600_CB2_names},
- { 128, 1272, 0x00000000, 0x00000000, 0x0000, 0, "R600_CB3", 7, r600_state_pm4_cb0, R600_CB3_names},
- { 128, 1273, 0x00000000, 0x00000000, 0x0000, 0, "R600_CB4", 7, r600_state_pm4_cb0, R600_CB4_names},
- { 128, 1274, 0x00000000, 0x00000000, 0x0000, 0, "R600_CB5", 7, r600_state_pm4_cb0, R600_CB5_names},
- { 128, 1275, 0x00000000, 0x00000000, 0x0000, 0, "R600_CB6", 7, r600_state_pm4_cb0, R600_CB6_names},
- { 128, 1276, 0x00000000, 0x00000000, 0x0000, 0, "R600_CB7", 7, r600_state_pm4_cb0, R600_CB7_names},
- { 128, 1277, 0x00000000, 0x00000000, 0x0000, 0, "R600_QUERY_BEGIN", 1, r600_state_pm4_query_begin, R600_VGT_EVENT_names},
- { 128, 1278, 0x00000000, 0x00000000, 0x0000, 0, "R600_QUERY_END", 1, r600_state_pm4_query_end, R600_VGT_EVENT_names},
- { 128, 1279, 0x00000000, 0x00000000, 0x0000, 0, "R600_DB", 6, r600_state_pm4_db, R600_DB_names},
- { 128, 1280, 0x00028e20, 0x00028e70, 0x0010, 0, "R600_UCP", 4, r600_state_pm4_generic, R600_UCP_names},
- { 128, 1286, 0x00000000, 0x00000000, 0x0000, 0, "R600_VGT", 11, r600_state_pm4_vgt, R600_VGT_names},
- { 128, 1287, 0x00000000, 0x00000000, 0x0000, 0, "R600_DRAW", 4, r600_state_pm4_draw, R600_DRAW_names},
-};
-
-static struct radeon_type R700_types[] = {
- { 128, 0, 0x00000000, 0x00000000, 0x0000, 0, "R600_CONFIG", 41, r700_state_pm4_config, R600_CONFIG_names},
- { 128, 1, 0x00000000, 0x00000000, 0x0000, 0, "R600_CB_CNTL", 18, r600_state_pm4_generic, R600_CB_CNTL_names},
- { 128, 2, 0x00000000, 0x00000000, 0x0000, 0, "R600_RASTERIZER", 21, r600_state_pm4_generic, R600_RASTERIZER_names},
- { 128, 3, 0x00000000, 0x00000000, 0x0000, 0, "R600_VIEWPORT", 9, r600_state_pm4_generic, R600_VIEWPORT_names},
- { 128, 4, 0x00000000, 0x00000000, 0x0000, 0, "R600_SCISSOR", 19, r600_state_pm4_generic, R600_SCISSOR_names},
- { 128, 5, 0x00000000, 0x00000000, 0x0000, 0, "R600_BLEND", 13, r600_state_pm4_generic, R600_BLEND_names},
- { 128, 6, 0x00000000, 0x00000000, 0x0000, 0, "R600_DSA", 16, r600_state_pm4_generic, R600_DSA_names},
- { 128, 7, 0x00000000, 0x00000000, 0x0000, 0, "R600_VS_SHADER", 49, r600_state_pm4_shader, R600_VS_SHADER_names},
- { 128, 8, 0x00000000, 0x00000000, 0x0000, 0, "R600_PS_SHADER", 39, r600_state_pm4_shader, R600_PS_SHADER_names},
- { 128, 9, 0x00030000, 0x00031000, 0x0010, 0, "R600_PS_CONSTANT", 4, r600_state_pm4_generic, R600_PS_CONSTANT_names},
- { 128, 265, 0x00031000, 0x00032000, 0x0010, 0, "R600_VS_CONSTANT", 4, r600_state_pm4_generic, R600_VS_CONSTANT_names},
- { 128, 521, 0x00038000, 0x00039180, 0x001C, 0, "R600_PS_RESOURCE", 7, r600_state_pm4_resource, R600_PS_RESOURCE_names},
- { 128, 681, 0x00039180, 0x0003A300, 0x001C, 0, "R600_VS_RESOURCE", 7, r600_state_pm4_resource, R600_VS_RESOURCE_names},
- { 128, 841, 0x00039180, 0x0003A300, 0x001C, 0, "R600_FS_RESOURCE", 7, r600_state_pm4_resource, R600_FS_RESOURCE_names},
- { 128, 1001, 0x00039180, 0x0003A300, 0x001C, 0, "R600_GS_RESOURCE", 7, r600_state_pm4_resource, R600_GS_RESOURCE_names},
- { 128, 1161, 0x0003C000, 0x0003C0D8, 0x000C, 0, "R600_PS_SAMPLER", 3, r600_state_pm4_generic, R600_PS_SAMPLER_names},
- { 128, 1179, 0x0003C0D8, 0x0003C1B0, 0x000C, 0, "R600_VS_SAMPLER", 3, r600_state_pm4_generic, R600_VS_SAMPLER_names},
- { 128, 1197, 0x0003C1B0, 0x0003C288, 0x000C, 0, "R600_GS_SAMPLER", 3, r600_state_pm4_generic, R600_GS_SAMPLER_names},
- { 128, 1215, 0x0000A400, 0x0000A520, 0x0010, 0, "R600_PS_SAMPLER_BORDER", 4, r600_state_pm4_generic, R600_PS_SAMPLER_BORDER_names},
- { 128, 1233, 0x0000A600, 0x0000A720, 0x0010, 0, "R600_VS_SAMPLER_BORDER", 4, r600_state_pm4_generic, R600_VS_SAMPLER_BORDER_names},
- { 128, 1251, 0x0000A800, 0x0000A920, 0x0010, 0, "R600_GS_SAMPLER_BORDER", 4, r600_state_pm4_generic, R600_GS_SAMPLER_BORDER_names},
- { 128, 1269, 0x00000000, 0x00000000, 0x0000, 0, "R600_CB0", 7, r700_state_pm4_cb0, R600_CB0_names},
- { 128, 1270, 0x00000000, 0x00000000, 0x0000, 0, "R600_CB1", 7, r600_state_pm4_cb0, R600_CB1_names},
- { 128, 1271, 0x00000000, 0x00000000, 0x0000, 0, "R600_CB2", 7, r600_state_pm4_cb0, R600_CB2_names},
- { 128, 1272, 0x00000000, 0x00000000, 0x0000, 0, "R600_CB3", 7, r600_state_pm4_cb0, R600_CB3_names},
- { 128, 1273, 0x00000000, 0x00000000, 0x0000, 0, "R600_CB4", 7, r600_state_pm4_cb0, R600_CB4_names},
- { 128, 1274, 0x00000000, 0x00000000, 0x0000, 0, "R600_CB5", 7, r600_state_pm4_cb0, R600_CB5_names},
- { 128, 1275, 0x00000000, 0x00000000, 0x0000, 0, "R600_CB6", 7, r600_state_pm4_cb0, R600_CB6_names},
- { 128, 1276, 0x00000000, 0x00000000, 0x0000, 0, "R600_CB7", 7, r600_state_pm4_cb0, R600_CB7_names},
- { 128, 1277, 0x00000000, 0x00000000, 0x0000, 0, "R600_QUERY_BEGIN", 1, r600_state_pm4_query_begin, R600_VGT_EVENT_names},
- { 128, 1278, 0x00000000, 0x00000000, 0x0000, 0, "R600_QUERY_END", 1, r600_state_pm4_query_end, R600_VGT_EVENT_names},
- { 128, 1279, 0x00000000, 0x00000000, 0x0000, 0, "R600_DB", 6, r700_state_pm4_db, R600_DB_names},
- { 128, 1280, 0x00028e20, 0x00028e70, 0x0010, 0, "R600_UCP", 4, r600_state_pm4_generic, R600_UCP_names},
- { 128, 1286, 0x00000000, 0x00000000, 0x0000, 0, "R600_VGT", 11, r600_state_pm4_vgt, R600_VGT_names},
- { 128, 1287, 0x00000000, 0x00000000, 0x0000, 0, "R600_DRAW", 4, r600_state_pm4_draw, R600_DRAW_names},
-};
-
#endif
diff --git a/src/gallium/winsys/r600/drm/radeon.c b/src/gallium/winsys/r600/drm/radeon.c
index 80b0a1d3972..2b16e3ce884 100644
--- a/src/gallium/winsys/r600/drm/radeon.c
+++ b/src/gallium/winsys/r600/drm/radeon.c
@@ -153,47 +153,3 @@ struct radeon *radeon_decref(struct radeon *radeon)
free(radeon);
return NULL;
}
-
-int radeon_reg_id(struct radeon *radeon, unsigned offset, unsigned *typeid, unsigned *stateid, unsigned *id)
-{
- unsigned i, j;
-
- for (i = 0; i < radeon->ntype; i++) {
- if (radeon->type[i].range_start) {
- if (offset >= radeon->type[i].range_start && offset < radeon->type[i].range_end) {
- *typeid = i;
- j = offset - radeon->type[i].range_start;
- j /= radeon->type[i].stride;
- *stateid = radeon->type[i].id + j;
- *id = (offset - radeon->type[i].range_start - radeon->type[i].stride * j) / 4;
- return 0;
- }
- } else {
- for (j = 0; j < radeon->type[i].nstates; j++) {
- if (radeon->type[i].regs[j].offset == offset) {
- *typeid = i;
- *stateid = radeon->type[i].id;
- *id = j;
- return 0;
- }
- }
- }
- }
- fprintf(stderr, "%s unknown register 0x%08X\n", __func__, offset);
- return -EINVAL;
-}
-
-unsigned radeon_type_from_id(struct radeon *radeon, unsigned id)
-{
- unsigned i;
-
- for (i = 0; i < radeon->ntype - 1; i++) {
- if (radeon->type[i].id == id)
- return i;
- if (id > radeon->type[i].id && id < radeon->type[i + 1].id)
- return i;
- }
- if (radeon->type[i].id == id)
- return i;
- return -1;
-}
diff --git a/src/gallium/winsys/r600/drm/radeon_ctx.c b/src/gallium/winsys/r600/drm/radeon_ctx.c
index bd050c4cf90..1a12c1023e1 100644
--- a/src/gallium/winsys/r600/drm/radeon_ctx.c
+++ b/src/gallium/winsys/r600/drm/radeon_ctx.c
@@ -216,7 +216,7 @@ static int radeon_ctx_state_schedule(struct radeon_ctx *ctx, struct radeon_state
r = radeon_ctx_reloc(ctx, state->bo[bid], cid,
&state->placement[bid * 2]);
if (r) {
- fprintf(stderr, "%s state %d failed to reloc\n", __func__, state->type);
+ fprintf(stderr, "%s state %d failed to reloc\n", __func__, state->stype->stype);
return r;
}
}
@@ -230,7 +230,7 @@ int radeon_ctx_set_query_state(struct radeon_ctx *ctx, struct radeon_state *stat
int r = 0;
/* !!! ONLY ACCEPT QUERY STATE HERE !!! */
- if (state->type != R600_QUERY_BEGIN_TYPE && state->type != R600_QUERY_END_TYPE) {
+ if (state->stype->stype != R600_STATE_QUERY_BEGIN && state->stype->stype != R600_STATE_QUERY_END) {
return -EINVAL;
}
r = radeon_state_pm4(state);
@@ -253,7 +253,7 @@ int radeon_ctx_set_query_state(struct radeon_ctx *ctx, struct radeon_state *stat
/* BEGIN/END query are balanced in the same cs so account for END
* END query when scheduling BEGIN query
*/
- if (state->type == R600_QUERY_BEGIN_TYPE) {
+ if (state->stype->stype == R600_STATE_QUERY_BEGIN) {
ctx->draw_cpm4 += state->cpm4 * 2;
}
return 0;
diff --git a/src/gallium/winsys/r600/drm/radeon_draw.c b/src/gallium/winsys/r600/drm/radeon_draw.c
index 4413ed79fbd..0eacdc74a03 100644
--- a/src/gallium/winsys/r600/drm/radeon_draw.c
+++ b/src/gallium/winsys/r600/drm/radeon_draw.c
@@ -74,12 +74,17 @@ struct radeon_draw *radeon_draw_decref(struct radeon_draw *draw)
int radeon_draw_set_new(struct radeon_draw *draw, struct radeon_state *state)
{
+ int id;
if (state == NULL)
return 0;
- if (state->type >= draw->radeon->ntype)
+
+ id = state->stype->base_id + (state->id + (state->stype->num * state->shader_index));
+ if (id > draw->radeon->nstate)
+ {
return -EINVAL;
- draw->state[state->id] = radeon_state_decref(draw->state[state->id]);
- draw->state[state->id] = state;
+ }
+ draw->state[id] = radeon_state_decref(draw->state[id]);
+ draw->state[id] = state;
return 0;
}
diff --git a/src/gallium/winsys/r600/drm/radeon_priv.h b/src/gallium/winsys/r600/drm/radeon_priv.h
index 96c0d060f7e..66ee5f21771 100644
--- a/src/gallium/winsys/r600/drm/radeon_priv.h
+++ b/src/gallium/winsys/r600/drm/radeon_priv.h
@@ -37,17 +37,20 @@ struct radeon_register {
char name[64];
};
-struct radeon_type {
- unsigned npm4;
- unsigned id;
- unsigned range_start;
- unsigned range_end;
- unsigned stride;
- unsigned immediate;
- char name[64];
- unsigned nstates;
- radeon_state_pm4_t pm4;
- const struct radeon_register *regs;
+struct radeon_sub_type {
+ int shader_type;
+ const struct radeon_register *regs;
+ unsigned nstates;
+};
+
+struct radeon_stype_info {
+ unsigned stype;
+ unsigned num;
+ unsigned stride;
+ radeon_state_pm4_t pm4;
+ struct radeon_sub_type reginfo[R600_SHADER_MAX];
+ unsigned base_id;
+ unsigned npm4;
};
struct radeon {
@@ -56,8 +59,8 @@ struct radeon {
unsigned device;
unsigned family;
unsigned nstate;
- unsigned ntype;
- const struct radeon_type *type;
+ unsigned nstype;
+ struct radeon_stype_info *stype;
};
extern struct radeon *radeon_new(int fd, unsigned device);
@@ -65,9 +68,6 @@ extern struct radeon *radeon_incref(struct radeon *radeon);
extern struct radeon *radeon_decref(struct radeon *radeon);
extern unsigned radeon_family_from_device(unsigned device);
extern int radeon_is_family_compatible(unsigned family1, unsigned family2);
-extern int radeon_reg_id(struct radeon *radeon, unsigned offset, unsigned *typeid, unsigned *stateid, unsigned *id);
-extern unsigned radeon_type_from_id(struct radeon *radeon, unsigned id);
-
int radeon_ctx_set_bo_new(struct radeon_ctx *ctx, struct radeon_bo *bo);
struct radeon_bo *radeon_ctx_get_bo(struct radeon_ctx *ctx, unsigned reloc);
diff --git a/src/gallium/winsys/r600/drm/radeon_state.c b/src/gallium/winsys/r600/drm/radeon_state.c
index 308288557a4..ef09fdfb960 100644
--- a/src/gallium/winsys/r600/drm/radeon_state.c
+++ b/src/gallium/winsys/r600/drm/radeon_state.c
@@ -32,29 +32,56 @@
/*
* state core functions
*/
-struct radeon_state *radeon_state(struct radeon *radeon, u32 type, u32 id)
+struct radeon_state *radeon_state_shader(struct radeon *radeon, u32 stype, u32 id, u32 shader_type)
{
struct radeon_state *state;
+ struct radeon_stype_info *found = NULL;
+ int i, j, shader_index = -1;
- if (type > radeon->ntype) {
- fprintf(stderr, "%s invalid type %d\n", __func__, type);
- return NULL;
+ /* traverse the stype array */
+ for (i = 0; i < radeon->nstype; i++) {
+ /* if the type doesn't match, if the shader doesn't match */
+ if (stype != radeon->stype[i].stype)
+ continue;
+ if (shader_type) {
+ for (j = 0; j < 4; j++) {
+ if (radeon->stype[i].reginfo[j].shader_type == shader_type) {
+ shader_index = j;
+ break;
+ }
+ }
+ if (shader_index == -1)
+ continue;
+ } else {
+ if (radeon->stype[i].reginfo[0].shader_type)
+ continue;
+ else
+ shader_index = 0;
+ }
+ if (id > radeon->stype[i].num)
+ continue;
+
+ found = &radeon->stype[i];
+ break;
}
- if (id > radeon->nstate) {
- fprintf(stderr, "%s invalid state id %d\n", __func__, id);
+
+ if (!found) {
+ fprintf(stderr, "%s invalid type %d/id %d/shader class %d\n", __func__, stype, id, shader_type);
return NULL;
}
+
state = calloc(1, sizeof(*state));
if (state == NULL)
return NULL;
+ state->stype = found;
state->radeon = radeon;
- state->type = type;
state->id = id;
+ state->shader_index = shader_index;
state->refcount = 1;
- state->npm4 = radeon->type[type].npm4;
- state->nstates = radeon->type[type].nstates;
+ state->npm4 = found->npm4;
+ state->nstates = found->reginfo[shader_index].nstates;
state->states = calloc(1, state->nstates * 4);
- state->pm4 = calloc(1, radeon->type[type].npm4 * 4);
+ state->pm4 = calloc(1, found->npm4 * 4);
if (state->states == NULL || state->pm4 == NULL) {
radeon_state_decref(state);
return NULL;
@@ -62,9 +89,14 @@ struct radeon_state *radeon_state(struct radeon *radeon, u32 type, u32 id)
return state;
}
+struct radeon_state *radeon_state(struct radeon *radeon, u32 type, u32 id)
+{
+ return radeon_state_shader(radeon, type, id, 0);
+}
+
struct radeon_state *radeon_state_duplicate(struct radeon_state *state)
{
- struct radeon_state *nstate = radeon_state(state->radeon, state->type, state->id);
+ struct radeon_state *nstate = radeon_state_shader(state->radeon, state->stype->stype, state->id, (1 << state->shader_index));
unsigned i;
if (state == NULL)
@@ -149,10 +181,10 @@ int radeon_state_pm4(struct radeon_state *state)
if (state == NULL || state->cpm4)
return 0;
- r = state->radeon->type[state->type].pm4(state);
+ r = state->stype->pm4(state);
if (r) {
fprintf(stderr, "%s failed to build PM4 for state(%d %d)\n",
- __func__, state->type, state->id);
+ __func__, state->stype->stype, state->id);
return r;
}
state->pm4_crc = crc32(state->pm4, state->cpm4 * 4);
generated by cgit v1.2.3 (git 2.39.1) at 2024-12-12 20:15:35 +0000