aboutsummaryrefslogtreecommitdiffstats
path: root/src/gallium/drivers
diff options
context:
space:
mode:
Diffstat (limited to 'src/gallium/drivers')
-rw-r--r--src/gallium/drivers/r600/evergreen_hw_context.c2
-rw-r--r--src/gallium/drivers/r600/evergreen_state.c13
-rw-r--r--src/gallium/drivers/r600/evergreend.h7
-rw-r--r--src/gallium/drivers/r600/r600_hw_context.c1
-rw-r--r--src/gallium/drivers/r600/r600_state.c9
-rw-r--r--src/gallium/drivers/r600/r600d.h6
6 files changed, 32 insertions, 6 deletions
diff --git a/src/gallium/drivers/r600/evergreen_hw_context.c b/src/gallium/drivers/r600/evergreen_hw_context.c
index 6494786b048..901cdbe6bad 100644
--- a/src/gallium/drivers/r600/evergreen_hw_context.c
+++ b/src/gallium/drivers/r600/evergreen_hw_context.c
@@ -192,6 +192,7 @@ static const struct r600_reg evergreen_context_reg_list[] = {
{R_028A6C_VGT_GS_OUT_PRIM_TYPE, 0, 0},
{R_028ABC_DB_HTILE_SURFACE, 0, 0},
{R_028B54_VGT_SHADER_STAGES_EN, 0, 0},
+ {R_028B70_DB_ALPHA_TO_MASK, 0, 0},
{R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL, 0, 0},
{R_028B7C_PA_SU_POLY_OFFSET_CLAMP, 0, 0},
{R_028B80_PA_SU_POLY_OFFSET_FRONT_SCALE, 0, 0},
@@ -454,6 +455,7 @@ static const struct r600_reg cayman_context_reg_list[] = {
{R_028A6C_VGT_GS_OUT_PRIM_TYPE, 0, 0},
{R_028ABC_DB_HTILE_SURFACE, 0, 0},
{R_028B54_VGT_SHADER_STAGES_EN, 0, 0},
+ {R_028B70_DB_ALPHA_TO_MASK, 0, 0},
{R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL, 0, 0},
{R_028B7C_PA_SU_POLY_OFFSET_CLAMP, 0, 0},
{R_028B80_PA_SU_POLY_OFFSET_FRONT_SCALE, 0, 0},
diff --git a/src/gallium/drivers/r600/evergreen_state.c b/src/gallium/drivers/r600/evergreen_state.c
index 98e0338f648..c16dcd45f28 100644
--- a/src/gallium/drivers/r600/evergreen_state.c
+++ b/src/gallium/drivers/r600/evergreen_state.c
@@ -743,6 +743,13 @@ static void *evergreen_create_blend_state(struct pipe_context *ctx,
r600_pipe_state_add_reg(rstate, R_028780_CB_BLEND0_CONTROL + i * 4, blend_cntl[i]);
}
+ r600_pipe_state_add_reg(rstate, R_028B70_DB_ALPHA_TO_MASK,
+ S_028B70_ALPHA_TO_MASK_ENABLE(state->alpha_to_coverage) |
+ S_028B70_ALPHA_TO_MASK_OFFSET0(2) |
+ S_028B70_ALPHA_TO_MASK_OFFSET1(2) |
+ S_028B70_ALPHA_TO_MASK_OFFSET2(2) |
+ S_028B70_ALPHA_TO_MASK_OFFSET3(2));
+
blend->alpha_to_one = state->alpha_to_one;
return rstate;
}
@@ -2011,7 +2018,6 @@ static void cayman_init_atom_start_cs(struct r600_context *rctx)
r600_store_context_reg(cb, R_028230_PA_SC_EDGERULE, 0xAAAAAAAA);
r600_store_context_reg(cb, R_028818_PA_CL_VTE_CNTL, 0x0000043F);
r600_store_context_reg(cb, R_028820_PA_CL_NANINF_CNTL, 0);
- r600_store_context_reg(cb, R_028B70_DB_ALPHA_TO_MASK, 0x0000AA00);
r600_store_context_reg_seq(cb, CM_R_028BDC_PA_SC_LINE_CNTL, 2);
r600_store_value(cb, 0x00000400); /* CM_R_028BDC_PA_SC_LINE_CNTL */
@@ -2496,8 +2502,6 @@ void evergreen_init_atom_start_cs(struct r600_context *rctx)
r600_store_value(cb, 0); /* R_028AC4_DB_SRESULTS_COMPARE_STATE1 */
r600_store_value(cb, 0); /* R_028AC8_DB_PRELOAD_CONTROL */
- r600_store_context_reg(cb, R_028B70_DB_ALPHA_TO_MASK, 0x0000AA00);
-
r600_store_context_reg_seq(cb, R_028C00_PA_SC_LINE_CNTL, 2);
r600_store_value(cb, 0x00000400); /* R_028C00_PA_SC_LINE_CNTL */
r600_store_value(cb, 0); /* R_028C04_PA_SC_AA_CONFIG */
@@ -2812,7 +2816,8 @@ void evergreen_update_dual_export_state(struct r600_context * rctx)
unsigned db_shader_control = rctx->ps_shader->current->db_shader_control |
S_02880C_DUAL_EXPORT_ENABLE(dual_export) |
- S_02880C_DB_SOURCE_FORMAT(db_source_format);
+ S_02880C_DB_SOURCE_FORMAT(db_source_format) |
+ S_02880C_ALPHA_TO_MASK_DISABLE(rctx->cb0_is_integer);
if (db_shader_control != rctx->db_shader_control) {
struct r600_pipe_state rstate;
diff --git a/src/gallium/drivers/r600/evergreend.h b/src/gallium/drivers/r600/evergreend.h
index 55061d42f9d..8558b21dcbe 100644
--- a/src/gallium/drivers/r600/evergreend.h
+++ b/src/gallium/drivers/r600/evergreend.h
@@ -749,6 +749,7 @@
#define V_02880C_EXPORT_DB_FULL 0x00
#define V_02880C_EXPORT_DB_FOUR16 0x01
#define V_02880C_EXPORT_DB_TWO 0x02
+#define S_02880C_ALPHA_TO_MASK_DISABLE(x) (((x) & 0x1) << 12)
#define R_028A00_PA_SU_POINT_SIZE 0x028A00
#define S_028A00_HEIGHT(x) (((x) & 0xFFFF) << 0)
@@ -1896,6 +1897,12 @@
#define R_028B50_VGT_STRMOUT_BASE_OFFSET_HI_3 0x028B50
#define R_028B54_VGT_SHADER_STAGES_EN 0x00028B54
#define R_028B70_DB_ALPHA_TO_MASK 0x00028B70
+#define S_028B70_ALPHA_TO_MASK_ENABLE(x) (((x) & 0x1) << 0)
+#define S_028B70_ALPHA_TO_MASK_OFFSET0(x) (((x) & 0x3) << 8)
+#define S_028B70_ALPHA_TO_MASK_OFFSET1(x) (((x) & 0x3) << 10)
+#define S_028B70_ALPHA_TO_MASK_OFFSET2(x) (((x) & 0x3) << 12)
+#define S_028B70_ALPHA_TO_MASK_OFFSET3(x) (((x) & 0x3) << 14)
+#define S_028B70_OFFSET_ROUND(x) (((x) & 0x1) << 16)
#define R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL 0x00028B78
#define S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(x) (((x) & 0xFF) << 0)
#define G_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(x) (((x) >> 0) & 0xFF)
diff --git a/src/gallium/drivers/r600/r600_hw_context.c b/src/gallium/drivers/r600/r600_hw_context.c
index a5e330f391d..09d8e174b3d 100644
--- a/src/gallium/drivers/r600/r600_hw_context.c
+++ b/src/gallium/drivers/r600/r600_hw_context.c
@@ -358,6 +358,7 @@ static const struct r600_reg r600_context_reg_list[] = {
{R_028A6C_VGT_GS_OUT_PRIM_TYPE, 0, 0},
{R_028D24_DB_HTILE_SURFACE, 0, 0},
{R_028D34_DB_PREFETCH_LIMIT, 0, 0},
+ {R_028D44_DB_ALPHA_TO_MASK, 0, 0},
{R_028204_PA_SC_WINDOW_SCISSOR_TL, 0, 0},
{R_028208_PA_SC_WINDOW_SCISSOR_BR, 0, 0},
{R_028250_PA_SC_VPORT_SCISSOR_0_TL, 0, 0},
diff --git a/src/gallium/drivers/r600/r600_state.c b/src/gallium/drivers/r600/r600_state.c
index 831630a83b1..ce6b12f4383 100644
--- a/src/gallium/drivers/r600/r600_state.c
+++ b/src/gallium/drivers/r600/r600_state.c
@@ -754,6 +754,13 @@ static void *r600_create_blend_state(struct pipe_context *ctx,
r600_pipe_state_add_reg(rstate, R_028804_CB_BLEND_CONTROL, bc);
}
+ r600_pipe_state_add_reg(rstate, R_028D44_DB_ALPHA_TO_MASK,
+ S_028D44_ALPHA_TO_MASK_ENABLE(state->alpha_to_coverage) |
+ S_028D44_ALPHA_TO_MASK_OFFSET0(2) |
+ S_028D44_ALPHA_TO_MASK_OFFSET1(2) |
+ S_028D44_ALPHA_TO_MASK_OFFSET2(2) |
+ S_028D44_ALPHA_TO_MASK_OFFSET3(2));
+
blend->alpha_to_one = state->alpha_to_one;
return rstate;
}
@@ -2120,8 +2127,6 @@ void r600_init_atom_start_cs(struct r600_context *rctx)
r600_store_value(cb, 0); /* R_028D2C_DB_SRESULTS_COMPARE_STATE1 */
r600_store_value(cb, 0); /* R_028D30_DB_PRELOAD_CONTROL */
- r600_store_context_reg(cb, R_028D44_DB_ALPHA_TO_MASK, 0xAA00);
-
r600_store_context_reg(cb, R_028820_PA_CL_NANINF_CNTL, 0);
r600_store_context_reg(cb, R_028A48_PA_SC_MPASS_PS_CNTL, 0);
diff --git a/src/gallium/drivers/r600/r600d.h b/src/gallium/drivers/r600/r600d.h
index c9f842270cc..e99ed1dadd7 100644
--- a/src/gallium/drivers/r600/r600d.h
+++ b/src/gallium/drivers/r600/r600d.h
@@ -2253,6 +2253,12 @@
#define R_028D2C_DB_SRESULTS_COMPARE_STATE1 0x028D2C
#define R_028D30_DB_PRELOAD_CONTROL 0x028D30
#define R_028D44_DB_ALPHA_TO_MASK 0x028D44
+#define S_028D44_ALPHA_TO_MASK_ENABLE(x) (((x) & 0x1) << 0)
+#define S_028D44_ALPHA_TO_MASK_OFFSET0(x) (((x) & 0x3) << 8)
+#define S_028D44_ALPHA_TO_MASK_OFFSET1(x) (((x) & 0x3) << 10)
+#define S_028D44_ALPHA_TO_MASK_OFFSET2(x) (((x) & 0x3) << 12)
+#define S_028D44_ALPHA_TO_MASK_OFFSET3(x) (((x) & 0x3) << 14)
+#define S_028D44_OFFSET_ROUND(x) (((x) & 0x1) << 16)
#define R_028868_SQ_PGM_RESOURCES_VS 0x028868
#define R_0286CC_SPI_PS_IN_CONTROL_0 0x0286CC
#define R_0286D0_SPI_PS_IN_CONTROL_1 0x0286D0
generated by cgit v1.2.3 (git 2.39.1) at 2024-12-05 00:00:53 +0000