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-rw-r--r--src/gallium/drivers/radeonsi/cik_sdma.c12
-rw-r--r--src/gallium/drivers/radeonsi/si_blit.c8
-rw-r--r--src/gallium/drivers/radeonsi/si_compute.c4
-rw-r--r--src/gallium/drivers/radeonsi/si_cp_dma.c2
-rw-r--r--src/gallium/drivers/radeonsi/si_debug.c4
-rw-r--r--src/gallium/drivers/radeonsi/si_descriptors.c12
-rw-r--r--src/gallium/drivers/radeonsi/si_dma.c8
-rw-r--r--src/gallium/drivers/radeonsi/si_hw_context.c10
-rw-r--r--src/gallium/drivers/radeonsi/si_perfcounter.c14
-rw-r--r--src/gallium/drivers/radeonsi/si_pipe.c24
-rw-r--r--src/gallium/drivers/radeonsi/si_shader.c16
-rw-r--r--src/gallium/drivers/radeonsi/si_shader_tgsi_setup.c4
-rw-r--r--src/gallium/drivers/radeonsi/si_state.c18
-rw-r--r--src/gallium/drivers/radeonsi/si_state_draw.c6
-rw-r--r--src/gallium/drivers/radeonsi/si_state_shaders.c18
-rw-r--r--src/gallium/drivers/radeonsi/si_uvd.c8
16 files changed, 84 insertions, 84 deletions
diff --git a/src/gallium/drivers/radeonsi/cik_sdma.c b/src/gallium/drivers/radeonsi/cik_sdma.c
index 8154d720dc2..aeaf9cbfe94 100644
--- a/src/gallium/drivers/radeonsi/cik_sdma.c
+++ b/src/gallium/drivers/radeonsi/cik_sdma.c
@@ -50,7 +50,7 @@ static void cik_sdma_copy_buffer(struct si_context *ctx,
src_offset += rsrc->gpu_address;
ncopy = DIV_ROUND_UP(size, CIK_SDMA_COPY_MAX_SIZE);
- r600_need_dma_space(&ctx->b, ncopy * 7, rdst, rsrc);
+ si_need_dma_space(&ctx->b, ncopy * 7, rdst, rsrc);
for (i = 0; i < ncopy; i++) {
csize = MIN2(size, CIK_SDMA_COPY_MAX_SIZE);
@@ -95,7 +95,7 @@ static void cik_sdma_clear_buffer(struct pipe_context *ctx,
/* the same maximum size as for copying */
ncopy = DIV_ROUND_UP(size, CIK_SDMA_COPY_MAX_SIZE);
- r600_need_dma_space(&sctx->b, ncopy * 5, rdst, NULL);
+ si_need_dma_space(&sctx->b, ncopy * 5, rdst, NULL);
for (i = 0; i < ncopy; i++) {
csize = MIN2(size, CIK_SDMA_COPY_MAX_SIZE);
@@ -194,7 +194,7 @@ static bool cik_sdma_copy_texture(struct si_context *sctx,
src_slice_pitch * bpp * (srcz + src_box->depth) <=
rsrc->resource.buf->size);
- if (!r600_prepare_for_dma_blit(&sctx->b, rdst, dst_level, dstx, dsty,
+ if (!si_prepare_for_dma_blit(&sctx->b, rdst, dst_level, dstx, dsty,
dstz, rsrc, src_level, src_box))
return false;
@@ -235,7 +235,7 @@ static bool cik_sdma_copy_texture(struct si_context *sctx,
srcy + copy_height != (1 << 14)))) {
struct radeon_winsys_cs *cs = sctx->b.dma.cs;
- r600_need_dma_space(&sctx->b, 13, &rdst->resource, &rsrc->resource);
+ si_need_dma_space(&sctx->b, 13, &rdst->resource, &rsrc->resource);
radeon_emit(cs, CIK_SDMA_PACKET(CIK_SDMA_OPCODE_COPY,
CIK_SDMA_COPY_SUB_OPCODE_LINEAR_SUB_WINDOW, 0) |
@@ -398,7 +398,7 @@ static bool cik_sdma_copy_texture(struct si_context *sctx,
struct radeon_winsys_cs *cs = sctx->b.dma.cs;
uint32_t direction = linear == rdst ? 1u << 31 : 0;
- r600_need_dma_space(&sctx->b, 14, &rdst->resource, &rsrc->resource);
+ si_need_dma_space(&sctx->b, 14, &rdst->resource, &rsrc->resource);
radeon_emit(cs, CIK_SDMA_PACKET(CIK_SDMA_OPCODE_COPY,
CIK_SDMA_COPY_SUB_OPCODE_TILED_SUB_WINDOW, 0) |
@@ -492,7 +492,7 @@ static bool cik_sdma_copy_texture(struct si_context *sctx,
dstx + copy_width != (1 << 14)))) {
struct radeon_winsys_cs *cs = sctx->b.dma.cs;
- r600_need_dma_space(&sctx->b, 15, &rdst->resource, &rsrc->resource);
+ si_need_dma_space(&sctx->b, 15, &rdst->resource, &rsrc->resource);
radeon_emit(cs, CIK_SDMA_PACKET(CIK_SDMA_OPCODE_COPY,
CIK_SDMA_COPY_SUB_OPCODE_T2T_SUB_WINDOW, 0));
diff --git a/src/gallium/drivers/radeonsi/si_blit.c b/src/gallium/drivers/radeonsi/si_blit.c
index 0ecfc83fe24..159893dfa11 100644
--- a/src/gallium/drivers/radeonsi/si_blit.c
+++ b/src/gallium/drivers/radeonsi/si_blit.c
@@ -350,7 +350,7 @@ si_decompress_depth(struct si_context *sctx,
*/
if (copy_planes &&
(tex->flushed_depth_texture ||
- r600_init_flushed_depth_texture(&sctx->b.b, &tex->resource.b.b, NULL))) {
+ si_init_flushed_depth_texture(&sctx->b.b, &tex->resource.b.b, NULL))) {
struct r600_texture *dst = tex->flushed_depth_texture;
unsigned fully_copied_levels;
unsigned levels = 0;
@@ -621,7 +621,7 @@ static void si_check_render_feedback_texture(struct si_context *sctx,
}
if (render_feedback)
- r600_texture_disable_dcc(&sctx->b, tex);
+ si_texture_disable_dcc(&sctx->b, tex);
}
static void si_check_render_feedback_textures(struct si_context *sctx,
@@ -835,7 +835,7 @@ static void si_clear(struct pipe_context *ctx, unsigned buffers,
zsbuf ? (struct r600_texture*)zsbuf->texture : NULL;
if (buffers & PIPE_CLEAR_COLOR) {
- evergreen_do_fast_color_clear(&sctx->b, fb,
+ si_do_fast_color_clear(&sctx->b, fb,
&sctx->framebuffer.atom, &buffers,
&sctx->framebuffer.dirty_cbufs,
color);
@@ -1175,7 +1175,7 @@ void si_resource_copy_region(struct pipe_context *ctx,
src_templ.format);
/* Initialize the surface. */
- dst_view = r600_create_surface_custom(ctx, dst, &dst_templ,
+ dst_view = si_create_surface_custom(ctx, dst, &dst_templ,
dst_width0, dst_height0,
dst_width, dst_height);
diff --git a/src/gallium/drivers/radeonsi/si_compute.c b/src/gallium/drivers/radeonsi/si_compute.c
index ca334949d77..3987eecca8e 100644
--- a/src/gallium/drivers/radeonsi/si_compute.c
+++ b/src/gallium/drivers/radeonsi/si_compute.c
@@ -175,7 +175,7 @@ static void *si_create_compute_state(
if ((sctx->b.debug.debug_message && !sctx->b.debug.async) ||
sctx->is_debug ||
- r600_can_dump_shader(&sscreen->b, PIPE_SHADER_COMPUTE))
+ si_can_dump_shader(&sscreen->b, PIPE_SHADER_COMPUTE))
si_create_compute_state_async(program, -1);
else
util_queue_add_job(&sscreen->shader_compiler_queue,
@@ -328,7 +328,7 @@ static bool si_setup_compute_scratch_buffer(struct si_context *sctx,
r600_resource_reference(&sctx->compute_scratch_buffer, NULL);
sctx->compute_scratch_buffer = (struct r600_resource*)
- r600_aligned_buffer_create(&sctx->screen->b.b,
+ si_aligned_buffer_create(&sctx->screen->b.b,
R600_RESOURCE_FLAG_UNMAPPABLE,
PIPE_USAGE_DEFAULT,
scratch_needed, 256);
diff --git a/src/gallium/drivers/radeonsi/si_cp_dma.c b/src/gallium/drivers/radeonsi/si_cp_dma.c
index 1aa1ef28c9c..064f6c02ccd 100644
--- a/src/gallium/drivers/radeonsi/si_cp_dma.c
+++ b/src/gallium/drivers/radeonsi/si_cp_dma.c
@@ -309,7 +309,7 @@ static void si_cp_dma_realign_engine(struct si_context *sctx, unsigned size,
sctx->scratch_buffer->b.b.width0 < scratch_size) {
r600_resource_reference(&sctx->scratch_buffer, NULL);
sctx->scratch_buffer = (struct r600_resource*)
- r600_aligned_buffer_create(&sctx->screen->b.b,
+ si_aligned_buffer_create(&sctx->screen->b.b,
R600_RESOURCE_FLAG_UNMAPPABLE,
PIPE_USAGE_DEFAULT,
scratch_size, 256);
diff --git a/src/gallium/drivers/radeonsi/si_debug.c b/src/gallium/drivers/radeonsi/si_debug.c
index 7a78b0b51f7..5075ccd26dd 100644
--- a/src/gallium/drivers/radeonsi/si_debug.c
+++ b/src/gallium/drivers/radeonsi/si_debug.c
@@ -540,14 +540,14 @@ static void si_dump_framebuffer(struct si_context *sctx, struct u_log_context *l
rtex = (struct r600_texture*)state->cbufs[i]->texture;
u_log_printf(log, COLOR_YELLOW "Color buffer %i:" COLOR_RESET "\n", i);
- r600_print_texture_info(sctx->b.screen, rtex, log);
+ si_print_texture_info(sctx->b.screen, rtex, log);
u_log_printf(log, "\n");
}
if (state->zsbuf) {
rtex = (struct r600_texture*)state->zsbuf->texture;
u_log_printf(log, COLOR_YELLOW "Depth-stencil buffer:" COLOR_RESET "\n");
- r600_print_texture_info(sctx->b.screen, rtex, log);
+ si_print_texture_info(sctx->b.screen, rtex, log);
u_log_printf(log, "\n");
}
}
diff --git a/src/gallium/drivers/radeonsi/si_descriptors.c b/src/gallium/drivers/radeonsi/si_descriptors.c
index b968a5057ac..26198d8c1f3 100644
--- a/src/gallium/drivers/radeonsi/si_descriptors.c
+++ b/src/gallium/drivers/radeonsi/si_descriptors.c
@@ -390,7 +390,7 @@ static void si_set_sampler_view_desc(struct si_context *sctx,
if (unlikely(!is_buffer && sview->dcc_incompatible)) {
if (vi_dcc_enabled(rtex, view->u.tex.first_level))
- if (!r600_texture_disable_dcc(&sctx->b, rtex))
+ if (!si_texture_disable_dcc(&sctx->b, rtex))
sctx->b.decompress_dcc(&sctx->b.b, rtex);
sview->dcc_incompatible = false;
@@ -674,7 +674,7 @@ static void si_set_shader_image_desc(struct si_context *ctx,
* The decompression is relatively cheap if the surface
* has been decompressed already.
*/
- if (!r600_texture_disable_dcc(&ctx->b, tex))
+ if (!si_texture_disable_dcc(&ctx->b, tex))
ctx->b.decompress_dcc(&ctx->b.b, tex);
}
@@ -1404,7 +1404,7 @@ static void si_set_streamout_targets(struct pipe_context *ctx,
*/
/* Set the VGT regs. */
- r600_set_streamout_targets(ctx, num_targets, targets, offsets);
+ si_common_set_streamout_targets(ctx, num_targets, targets, offsets);
/* Set the shader resources.*/
for (i = 0; i < num_targets; i++) {
@@ -1636,10 +1636,10 @@ static void si_rebind_buffer(struct pipe_context *ctx, struct pipe_resource *buf
/* Update the streamout state. */
if (sctx->b.streamout.begin_emitted)
- r600_emit_streamout_end(&sctx->b);
+ si_emit_streamout_end(&sctx->b);
sctx->b.streamout.append_bitmask =
sctx->b.streamout.enabled_mask;
- r600_streamout_buffers_dirty(&sctx->b);
+ si_streamout_buffers_dirty(&sctx->b);
}
}
@@ -1795,7 +1795,7 @@ static void si_invalidate_buffer(struct pipe_context *ctx, struct pipe_resource
uint64_t old_va = rbuffer->gpu_address;
/* Reallocate the buffer in the same pipe_resource. */
- r600_alloc_resource(&sctx->screen->b, rbuffer);
+ si_alloc_resource(&sctx->screen->b, rbuffer);
si_rebind_buffer(ctx, buf, old_va);
}
diff --git a/src/gallium/drivers/radeonsi/si_dma.c b/src/gallium/drivers/radeonsi/si_dma.c
index af639a532e8..9e3a3751c18 100644
--- a/src/gallium/drivers/radeonsi/si_dma.c
+++ b/src/gallium/drivers/radeonsi/si_dma.c
@@ -62,7 +62,7 @@ static void si_dma_copy_buffer(struct si_context *ctx,
}
ncopy = DIV_ROUND_UP(size, max_size);
- r600_need_dma_space(&ctx->b, ncopy * 5, rdst, rsrc);
+ si_need_dma_space(&ctx->b, ncopy * 5, rdst, rsrc);
for (i = 0; i < ncopy; i++) {
count = MIN2(size, max_size);
@@ -104,7 +104,7 @@ static void si_dma_clear_buffer(struct pipe_context *ctx,
/* the same maximum size as for copying */
ncopy = DIV_ROUND_UP(size, SI_DMA_COPY_MAX_DWORD_ALIGNED_SIZE);
- r600_need_dma_space(&sctx->b, ncopy * 4, rdst, NULL);
+ si_need_dma_space(&sctx->b, ncopy * 4, rdst, NULL);
for (i = 0; i < ncopy; i++) {
csize = MIN2(size, SI_DMA_COPY_MAX_DWORD_ALIGNED_SIZE);
@@ -193,7 +193,7 @@ static void si_dma_copy_tile(struct si_context *ctx,
mt = G_009910_MICRO_TILE_MODE(tile_mode);
size = copy_height * pitch;
ncopy = DIV_ROUND_UP(size, SI_DMA_COPY_MAX_DWORD_ALIGNED_SIZE);
- r600_need_dma_space(&ctx->b, ncopy * 9, &rdst->resource, &rsrc->resource);
+ si_need_dma_space(&ctx->b, ncopy * 9, &rdst->resource, &rsrc->resource);
for (i = 0; i < ncopy; i++) {
cheight = copy_height;
@@ -261,7 +261,7 @@ static void si_dma_copy(struct pipe_context *ctx,
goto fallback;
if (src_box->depth > 1 ||
- !r600_prepare_for_dma_blit(&sctx->b, rdst, dst_level, dstx, dsty,
+ !si_prepare_for_dma_blit(&sctx->b, rdst, dst_level, dstx, dsty,
dstz, rsrc, src_level, src_box))
goto fallback;
diff --git a/src/gallium/drivers/radeonsi/si_hw_context.c b/src/gallium/drivers/radeonsi/si_hw_context.c
index d090eea52b8..dafb3bfa5fe 100644
--- a/src/gallium/drivers/radeonsi/si_hw_context.c
+++ b/src/gallium/drivers/radeonsi/si_hw_context.c
@@ -29,7 +29,7 @@
void si_destroy_saved_cs(struct si_saved_cs *scs)
{
- radeon_clear_saved_cs(&scs->gfx);
+ si_clear_saved_cs(&scs->gfx);
r600_resource_reference(&scs->trace_buf, NULL);
free(scs);
}
@@ -80,7 +80,7 @@ void si_context_gfx_flush(void *context, unsigned flags,
if (!radeon_emitted(cs, ctx->b.initial_gfx_cs_size))
return;
- if (r600_check_device_reset(&ctx->b))
+ if (si_check_device_reset(&ctx->b))
return;
if (ctx->screen->b.debug_flags & DBG_CHECK_VM)
@@ -98,7 +98,7 @@ void si_context_gfx_flush(void *context, unsigned flags,
ctx->gfx_flush_in_progress = true;
- r600_preflush_suspend_features(&ctx->b);
+ si_preflush_suspend_features(&ctx->b);
ctx->b.flags |= SI_CONTEXT_CS_PARTIAL_FLUSH |
SI_CONTEXT_PS_PARTIAL_FLUSH;
@@ -115,7 +115,7 @@ void si_context_gfx_flush(void *context, unsigned flags,
si_log_hw_flush(ctx);
/* Save the IB for debug contexts. */
- radeon_save_cs(ws, cs, &ctx->current_saved_cs->gfx, true);
+ si_save_cs(ws, cs, &ctx->current_saved_cs->gfx, true);
ctx->current_saved_cs->flushed = true;
}
@@ -260,7 +260,7 @@ void si_begin_new_cs(struct si_context *ctx)
&ctx->scratch_buffer->b.b);
}
- r600_postflush_resume_features(&ctx->b);
+ si_postflush_resume_features(&ctx->b);
assert(!ctx->b.gfx.cs->prev_dw);
ctx->b.initial_gfx_cs_size = ctx->b.gfx.cs->current.cdw;
diff --git a/src/gallium/drivers/radeonsi/si_perfcounter.c b/src/gallium/drivers/radeonsi/si_perfcounter.c
index 4a543ea2449..cb3377a9737 100644
--- a/src/gallium/drivers/radeonsi/si_perfcounter.c
+++ b/src/gallium/drivers/radeonsi/si_perfcounter.c
@@ -614,10 +614,10 @@ static void si_pc_emit_stop(struct r600_common_context *ctx,
{
struct radeon_winsys_cs *cs = ctx->gfx.cs;
- r600_gfx_write_event_eop(ctx, EVENT_TYPE_BOTTOM_OF_PIPE_TS, 0,
+ si_gfx_write_event_eop(ctx, EVENT_TYPE_BOTTOM_OF_PIPE_TS, 0,
EOP_DATA_SEL_VALUE_32BIT,
buffer, va, 0, R600_NOT_QUERY);
- r600_gfx_wait_fence(ctx, va, 0, 0xffffffff);
+ si_gfx_wait_fence(ctx, va, 0, 0xffffffff);
radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
radeon_emit(cs, EVENT_TYPE(EVENT_TYPE_PERFCOUNTER_SAMPLE) | EVENT_INDEX(0));
@@ -676,7 +676,7 @@ static void si_pc_emit_read(struct r600_common_context *ctx,
static void si_pc_cleanup(struct r600_common_screen *rscreen)
{
- r600_perfcounters_do_destroy(rscreen->perfcounters);
+ si_perfcounters_do_destroy(rscreen->perfcounters);
rscreen->perfcounters = NULL;
}
@@ -717,7 +717,7 @@ void si_init_perfcounters(struct si_screen *screen)
return;
pc->num_start_cs_dwords = 14;
- pc->num_stop_cs_dwords = 14 + r600_gfx_write_fence_dwords(&screen->b);
+ pc->num_stop_cs_dwords = 14 + si_gfx_write_fence_dwords(&screen->b);
pc->num_instance_cs_dwords = 3;
pc->num_shaders_cs_dwords = 4;
@@ -734,7 +734,7 @@ void si_init_perfcounters(struct si_screen *screen)
pc->emit_read = si_pc_emit_read;
pc->cleanup = si_pc_cleanup;
- if (!r600_perfcounters_init(pc, num_blocks))
+ if (!si_perfcounters_init(pc, num_blocks))
goto error;
for (i = 0; i < num_blocks; ++i) {
@@ -746,7 +746,7 @@ void si_init_perfcounters(struct si_screen *screen)
instances = 2;
}
- r600_perfcounters_add_block(&screen->b, pc,
+ si_perfcounters_add_block(&screen->b, pc,
block->b->name,
block->b->flags,
block->b->num_counters,
@@ -759,5 +759,5 @@ void si_init_perfcounters(struct si_screen *screen)
return;
error:
- r600_perfcounters_do_destroy(pc);
+ si_perfcounters_do_destroy(pc);
}
diff --git a/src/gallium/drivers/radeonsi/si_pipe.c b/src/gallium/drivers/radeonsi/si_pipe.c
index 2eacc5d69ed..97e38472409 100644
--- a/src/gallium/drivers/radeonsi/si_pipe.c
+++ b/src/gallium/drivers/radeonsi/si_pipe.c
@@ -88,7 +88,7 @@ static void si_destroy_context(struct pipe_context *context)
if (sctx->blitter)
util_blitter_destroy(sctx->blitter);
- r600_common_context_cleanup(&sctx->b);
+ si_common_context_cleanup(&sctx->b);
LLVMDisposeTargetMachine(sctx->tm);
@@ -145,7 +145,7 @@ si_create_llvm_target_machine(struct si_screen *sscreen)
sscreen->b.debug_flags & DBG_SI_SCHED ? ",+si-scheduler" : "");
return LLVMCreateTargetMachine(ac_get_llvm_target(triple), triple,
- r600_get_llvm_processor_name(sscreen->b.family),
+ si_get_llvm_processor_name(sscreen->b.family),
features,
LLVMCodeGenLevelDefault,
LLVMRelocDefault,
@@ -185,7 +185,7 @@ static struct pipe_context *si_create_context(struct pipe_screen *screen,
sctx->screen = sscreen; /* Easy accessing of screen/winsys. */
sctx->is_debug = (flags & PIPE_CONTEXT_DEBUG) != 0;
- if (!r600_common_context_init(&sctx->b, &sscreen->b, flags))
+ if (!si_common_context_init(&sctx->b, &sscreen->b, flags))
goto fail;
if (sscreen->b.info.drm_major == 3)
@@ -243,7 +243,7 @@ static struct pipe_context *si_create_context(struct pipe_screen *screen,
sctx->blitter = util_blitter_create(&sctx->b.b);
if (sctx->blitter == NULL)
goto fail;
- sctx->blitter->draw_rectangle = r600_draw_rectangle;
+ sctx->blitter->draw_rectangle = si_draw_rectangle;
sctx->sample_mask.sample_mask = 0xffff;
@@ -271,7 +271,7 @@ static struct pipe_context *si_create_context(struct pipe_screen *screen,
* if NUM_RECORDS == 0). We need to use a dummy buffer instead. */
if (sctx->b.chip_class == CIK) {
sctx->null_const_buf.buffer =
- r600_aligned_buffer_create(screen,
+ si_aligned_buffer_create(screen,
R600_RESOURCE_FLAG_UNMAPPABLE,
PIPE_USAGE_DEFAULT, 16,
sctx->screen->b.info.tcc_cache_line_size);
@@ -375,7 +375,7 @@ static struct pipe_context *si_pipe_create_context(struct pipe_screen *screen,
return ctx;
return threaded_context_create(ctx, &sscreen->b.pool_transfers,
- r600_replace_buffer_storage,
+ si_replace_buffer_storage,
&((struct si_context*)ctx)->b.tc);
}
@@ -835,13 +835,13 @@ static void si_destroy_screen(struct pipe_screen* pscreen)
struct si_shader_part *part = parts[i];
parts[i] = part->next;
- radeon_shader_binary_clean(&part->binary);
+ si_radeon_shader_binary_clean(&part->binary);
FREE(part);
}
}
mtx_destroy(&sscreen->shader_parts_mutex);
si_destroy_shader_cache(sscreen);
- r600_destroy_common_screen(&sscreen->b);
+ si_destroy_common_screen(&sscreen->b);
}
static bool si_init_gs_info(struct si_screen *sscreen)
@@ -885,7 +885,7 @@ static void si_handle_env_var_force_family(struct si_screen *sscreen)
return;
for (i = CHIP_TAHITI; i < CHIP_LAST; i++) {
- if (!strcmp(family, r600_get_llvm_processor_name(i))) {
+ if (!strcmp(family, si_get_llvm_processor_name(i))) {
/* Override family and chip_class. */
sscreen->b.family = sscreen->b.info.family = i;
@@ -969,7 +969,7 @@ struct pipe_screen *radeonsi_screen_create(struct radeon_winsys *ws,
sscreen->b.b.get_compiler_options = si_get_compiler_options;
sscreen->b.b.get_device_uuid = radeonsi_get_device_uuid;
sscreen->b.b.get_driver_uuid = radeonsi_get_driver_uuid;
- sscreen->b.b.resource_create = r600_resource_create_common;
+ sscreen->b.b.resource_create = si_resource_create_common;
si_init_screen_state_functions(sscreen);
@@ -982,7 +982,7 @@ struct pipe_screen *radeonsi_screen_create(struct radeon_winsys *ws,
if (driQueryOptionb(config->options, "radeonsi_enable_sisched"))
sscreen->b.debug_flags |= DBG_SI_SCHED;
- if (!r600_common_screen_init(&sscreen->b, ws) ||
+ if (!si_common_screen_init(&sscreen->b, ws) ||
!si_init_gs_info(sscreen) ||
!si_init_shader_cache(sscreen)) {
FREE(sscreen);
@@ -1110,7 +1110,7 @@ struct pipe_screen *radeonsi_screen_create(struct radeon_winsys *ws,
sscreen->b.aux_context = si_create_context(&sscreen->b.b, 0);
if (sscreen->b.debug_flags & DBG_TEST_DMA)
- r600_test_dma(&sscreen->b);
+ si_test_dma(&sscreen->b);
if (sscreen->b.debug_flags & (DBG_TEST_VMFAULT_CP |
DBG_TEST_VMFAULT_SDMA |
diff --git a/src/gallium/drivers/radeonsi/si_shader.c b/src/gallium/drivers/radeonsi/si_shader.c
index aea199d3efd..46ea1c20825 100644
--- a/src/gallium/drivers/radeonsi/si_shader.c
+++ b/src/gallium/drivers/radeonsi/si_shader.c
@@ -5109,7 +5109,7 @@ static void si_shader_dump_stats(struct si_screen *sscreen,
max_simd_waves = MIN2(max_simd_waves, 16384 / lds_per_wave);
if (!check_debug_option ||
- r600_can_dump_shader(&sscreen->b, processor)) {
+ si_can_dump_shader(&sscreen->b, processor)) {
if (processor == PIPE_SHADER_FRAGMENT) {
fprintf(file, "*** SHADER CONFIG ***\n"
"SPI_PS_INPUT_ADDR = 0x%04x\n"
@@ -5181,7 +5181,7 @@ void si_shader_dump(struct si_screen *sscreen, const struct si_shader *shader,
FILE *file, bool check_debug_option)
{
if (!check_debug_option ||
- r600_can_dump_shader(&sscreen->b, processor))
+ si_can_dump_shader(&sscreen->b, processor))
si_dump_shader_key(processor, shader, file);
if (!check_debug_option && shader->binary.llvm_ir_string) {
@@ -5198,7 +5198,7 @@ void si_shader_dump(struct si_screen *sscreen, const struct si_shader *shader,
}
if (!check_debug_option ||
- (r600_can_dump_shader(&sscreen->b, processor) &&
+ (si_can_dump_shader(&sscreen->b, processor) &&
!(sscreen->b.debug_flags & DBG_NO_ASM))) {
fprintf(file, "\n%s:\n", si_get_shader_name(shader, processor));
@@ -5236,7 +5236,7 @@ static int si_compile_llvm(struct si_screen *sscreen,
int r = 0;
unsigned count = p_atomic_inc_return(&sscreen->b.num_compilations);
- if (r600_can_dump_shader(&sscreen->b, processor)) {
+ if (si_can_dump_shader(&sscreen->b, processor)) {
fprintf(stderr, "radeonsi: Compiling shader %d\n", count);
if (!(sscreen->b.debug_flags & (DBG_NO_IR | DBG_PREOPT_IR))) {
@@ -5434,7 +5434,7 @@ si_generate_gs_copy_shader(struct si_screen *sscreen,
debug, PIPE_SHADER_GEOMETRY,
"GS Copy Shader");
if (!r) {
- if (r600_can_dump_shader(&sscreen->b, PIPE_SHADER_GEOMETRY))
+ if (si_can_dump_shader(&sscreen->b, PIPE_SHADER_GEOMETRY))
fprintf(stderr, "GS Copy Shader:\n");
si_shader_dump(sscreen, ctx.shader, debug,
PIPE_SHADER_GEOMETRY, stderr, true);
@@ -6352,7 +6352,7 @@ int si_compile_tgsi_shader(struct si_screen *sscreen,
/* Dump TGSI code before doing TGSI->LLVM conversion in case the
* conversion fails. */
- if (r600_can_dump_shader(&sscreen->b, sel->info.processor) &&
+ if (si_can_dump_shader(&sscreen->b, sel->info.processor) &&
!(sscreen->b.debug_flags & DBG_NO_TGSI)) {
if (sel->tokens)
tgsi_dump(sel->tokens, 0);
@@ -6561,7 +6561,7 @@ int si_compile_tgsi_shader(struct si_screen *sscreen,
si_optimize_vs_outputs(&ctx);
if ((debug && debug->debug_message) ||
- r600_can_dump_shader(&sscreen->b, ctx.type))
+ si_can_dump_shader(&sscreen->b, ctx.type))
si_count_scratch_private_memory(&ctx);
/* Compile to bytecode. */
@@ -7750,7 +7750,7 @@ void si_shader_destroy(struct si_shader *shader)
r600_resource_reference(&shader->bo, NULL);
if (!shader->is_binary_shared)
- radeon_shader_binary_clean(&shader->binary);
+ si_radeon_shader_binary_clean(&shader->binary);
free(shader->shader_log);
}
diff --git a/src/gallium/drivers/radeonsi/si_shader_tgsi_setup.c b/src/gallium/drivers/radeonsi/si_shader_tgsi_setup.c
index 0ad394d461e..be7a0b97489 100644
--- a/src/gallium/drivers/radeonsi/si_shader_tgsi_setup.c
+++ b/src/gallium/drivers/radeonsi/si_shader_tgsi_setup.c
@@ -1388,7 +1388,7 @@ void si_llvm_optimize_module(struct si_shader_context *ctx)
/* Dump LLVM IR before any optimization passes */
if (ctx->screen->b.debug_flags & DBG_PREOPT_IR &&
- r600_can_dump_shader(&ctx->screen->b, ctx->type))
+ si_can_dump_shader(&ctx->screen->b, ctx->type))
LLVMDumpModule(ctx->gallivm.module);
/* Create the pass manager */
@@ -1397,7 +1397,7 @@ void si_llvm_optimize_module(struct si_shader_context *ctx)
target_library_info = gallivm_create_target_library_info(triple);
LLVMAddTargetLibraryInfo(target_library_info, gallivm->passmgr);
- if (r600_extra_shader_checks(&ctx->screen->b, ctx->type))
+ if (si_extra_shader_checks(&ctx->screen->b, ctx->type))
LLVMAddVerifierPass(gallivm->passmgr);
LLVMAddAlwaysInlinerPass(gallivm->passmgr);
diff --git a/src/gallium/drivers/radeonsi/si_state.c b/src/gallium/drivers/radeonsi/si_state.c
index 3135566cd63..a468a1d35a2 100644
--- a/src/gallium/drivers/radeonsi/si_state.c
+++ b/src/gallium/drivers/radeonsi/si_state.c
@@ -1003,7 +1003,7 @@ static void si_bind_rs_state(struct pipe_context *ctx, void *state)
sctx->current_vs_state &= C_VS_STATE_CLAMP_VERTEX_COLOR;
sctx->current_vs_state |= S_VS_STATE_CLAMP_VERTEX_COLOR(rs->clamp_vertex_color);
- r600_viewport_set_rast_deps(&sctx->b, rs->scissor_enable, rs->clip_halfz);
+ si_viewport_set_rast_deps(&sctx->b, rs->scissor_enable, rs->clip_halfz);
si_pm4_bind_state(sctx, rasterizer, rs);
si_update_poly_offset_state(sctx);
@@ -2093,7 +2093,7 @@ static unsigned si_is_vertex_format_supported(struct pipe_screen *screen,
static bool si_is_colorbuffer_format_supported(enum pipe_format format)
{
return si_translate_colorformat(format) != V_028C70_COLOR_INVALID &&
- r600_translate_colorswap(format, false) != ~0U;
+ si_translate_colorswap(format, false) != ~0U;
}
static bool si_is_zs_format_supported(enum pipe_format format)
@@ -2354,7 +2354,7 @@ static void si_initialize_color_surface(struct si_context *sctx,
R600_ERR("Invalid CB format: %d, disabling CB.\n", surf->base.format);
}
assert(format != V_028C70_COLOR_INVALID);
- swap = r600_translate_colorswap(surf->base.format, false);
+ swap = si_translate_colorswap(surf->base.format, false);
endian = si_colorformat_endian_swap(format);
/* blend clamp should be set for all NORM/SRGB types */
@@ -2719,7 +2719,7 @@ static void si_set_framebuffer_state(struct pipe_context *ctx,
}
if (vi_dcc_enabled(rtex, surf->base.u.tex.level))
- if (!r600_texture_disable_dcc(&sctx->b, rtex))
+ if (!si_texture_disable_dcc(&sctx->b, rtex))
sctx->b.decompress_dcc(ctx, rtex);
surf->dcc_incompatible = false;
@@ -3184,7 +3184,7 @@ static void si_emit_msaa_sample_locs(struct si_context *sctx,
if (nr_samples != sctx->msaa_sample_locs.nr_samples) {
sctx->msaa_sample_locs.nr_samples = nr_samples;
- cayman_emit_msaa_sample_locs(cs, nr_samples);
+ si_common_emit_msaa_sample_locs(cs, nr_samples);
}
if (sctx->b.family >= CHIP_POLARIS10) {
@@ -3296,7 +3296,7 @@ static void si_emit_msaa_config(struct si_context *sctx, struct r600_atom *atom)
S_028A4C_FORCE_EOV_CNTDWN_ENABLE(1) |
S_028A4C_FORCE_EOV_REZ_ENABLE(1);
- cayman_emit_msaa_config(cs, sctx->framebuffer.nr_samples,
+ si_common_emit_msaa_config(cs, sctx->framebuffer.nr_samples,
sctx->ps_iter_samples,
sctx->smoothing_enabled ? SI_NUM_SMOOTH_AA_SAMPLES : 0,
sc_mode_cntl_1);
@@ -3629,7 +3629,7 @@ si_make_texture_descriptor(struct si_screen *screen,
}
if (tex->dcc_offset) {
- unsigned swap = r600_translate_colorswap(pipe_format, false);
+ unsigned swap = si_translate_colorswap(pipe_format, false);
state[6] = S_008F28_ALPHA_IS_ON_MSB(swap <= 1);
} else {
@@ -3805,7 +3805,7 @@ si_create_sampler_view_custom(struct pipe_context *ctx,
/* Depth/stencil texturing sometimes needs separate texture. */
if (tmp->is_depth && !r600_can_sample_zs(tmp, view->is_stencil_sampler)) {
if (!tmp->flushed_depth_texture &&
- !r600_init_flushed_depth_texture(ctx, texture, NULL)) {
+ !si_init_flushed_depth_texture(ctx, texture, NULL)) {
pipe_resource_reference(&view->base.texture, NULL);
FREE(view);
return NULL;
@@ -4413,7 +4413,7 @@ void si_init_state_functions(struct si_context *sctx)
sctx->b.b.set_stencil_ref = si_set_stencil_ref;
sctx->b.b.set_framebuffer_state = si_set_framebuffer_state;
- sctx->b.b.get_sample_position = cayman_get_sample_position;
+ sctx->b.b.get_sample_position = si_get_sample_position;
sctx->b.b.create_sampler_state = si_create_sampler_state;
sctx->b.b.delete_sampler_state = si_delete_sampler_state;
diff --git a/src/gallium/drivers/radeonsi/si_state_draw.c b/src/gallium/drivers/radeonsi/si_state_draw.c
index 05ed85475bf..897c86b0544 100644
--- a/src/gallium/drivers/radeonsi/si_state_draw.c
+++ b/src/gallium/drivers/radeonsi/si_state_draw.c
@@ -893,7 +893,7 @@ void si_emit_cache_flush(struct si_context *sctx)
/* Necessary for DCC */
if (rctx->chip_class == VI)
- r600_gfx_write_event_eop(rctx, V_028A90_FLUSH_AND_INV_CB_DATA_TS,
+ si_gfx_write_event_eop(rctx, V_028A90_FLUSH_AND_INV_CB_DATA_TS,
0, EOP_DATA_SEL_DISCARD, NULL,
0, 0, R600_NOT_QUERY);
}
@@ -1008,11 +1008,11 @@ void si_emit_cache_flush(struct si_context *sctx)
va = sctx->wait_mem_scratch->gpu_address;
sctx->wait_mem_number++;
- r600_gfx_write_event_eop(rctx, cb_db_event, tc_flags,
+ si_gfx_write_event_eop(rctx, cb_db_event, tc_flags,
EOP_DATA_SEL_VALUE_32BIT,
sctx->wait_mem_scratch, va,
sctx->wait_mem_number, R600_NOT_QUERY);
- r600_gfx_wait_fence(rctx, va, sctx->wait_mem_number, 0xffffffff);
+ si_gfx_wait_fence(rctx, va, sctx->wait_mem_number, 0xffffffff);
}
/* Make sure ME is idle (it executes most packets) before continuing.
diff --git a/src/gallium/drivers/radeonsi/si_state_shaders.c b/src/gallium/drivers/radeonsi/si_state_shaders.c
index 53a60ba11ed..788631c9863 100644
--- a/src/gallium/drivers/radeonsi/si_state_shaders.c
+++ b/src/gallium/drivers/radeonsi/si_state_shaders.c
@@ -2226,7 +2226,7 @@ static void *si_create_shader_selector(struct pipe_context *ctx,
if ((sctx->b.debug.debug_message && !sctx->b.debug.async) ||
sctx->is_debug ||
- r600_can_dump_shader(&sscreen->b, sel->info.processor))
+ si_can_dump_shader(&sscreen->b, sel->info.processor))
si_init_shader_selector_async(sel, -1);
else
util_queue_add_job(&sscreen->shader_compiler_queue, sel,
@@ -2299,7 +2299,7 @@ static void si_bind_vs_shader(struct pipe_context *ctx, void *state)
sctx->vs_shader.current = sel ? sel->first_variant : NULL;
si_update_common_shader_state(sctx);
- r600_update_vs_writes_viewport_index(&sctx->b, si_get_vs_info(sctx));
+ si_update_vs_writes_viewport_index(&sctx->b, si_get_vs_info(sctx));
si_set_active_descriptors_for_shader(sctx, sel);
si_update_streamout_state(sctx);
si_update_clip_regs(sctx, old_hw_vs, old_hw_vs_variant,
@@ -2342,7 +2342,7 @@ static void si_bind_gs_shader(struct pipe_context *ctx, void *state)
if (sctx->ia_multi_vgt_param_key.u.uses_tess)
si_update_tess_uses_prim_id(sctx);
}
- r600_update_vs_writes_viewport_index(&sctx->b, si_get_vs_info(sctx));
+ si_update_vs_writes_viewport_index(&sctx->b, si_get_vs_info(sctx));
si_set_active_descriptors_for_shader(sctx, sel);
si_update_streamout_state(sctx);
si_update_clip_regs(sctx, old_hw_vs, old_hw_vs_variant,
@@ -2393,7 +2393,7 @@ static void si_bind_tes_shader(struct pipe_context *ctx, void *state)
si_shader_change_notify(sctx);
sctx->last_tes_sh_base = -1; /* invalidate derived tess state */
}
- r600_update_vs_writes_viewport_index(&sctx->b, si_get_vs_info(sctx));
+ si_update_vs_writes_viewport_index(&sctx->b, si_get_vs_info(sctx));
si_set_active_descriptors_for_shader(sctx, sel);
si_update_streamout_state(sctx);
si_update_clip_regs(sctx, old_hw_vs, old_hw_vs_variant,
@@ -2710,7 +2710,7 @@ static bool si_update_gs_ring_buffers(struct si_context *sctx)
if (update_esgs) {
pipe_resource_reference(&sctx->esgs_ring, NULL);
sctx->esgs_ring =
- r600_aligned_buffer_create(sctx->b.b.screen,
+ si_aligned_buffer_create(sctx->b.b.screen,
R600_RESOURCE_FLAG_UNMAPPABLE,
PIPE_USAGE_DEFAULT,
esgs_ring_size, alignment);
@@ -2721,7 +2721,7 @@ static bool si_update_gs_ring_buffers(struct si_context *sctx)
if (update_gsvs) {
pipe_resource_reference(&sctx->gsvs_ring, NULL);
sctx->gsvs_ring =
- r600_aligned_buffer_create(sctx->b.b.screen,
+ si_aligned_buffer_create(sctx->b.b.screen,
R600_RESOURCE_FLAG_UNMAPPABLE,
PIPE_USAGE_DEFAULT,
gsvs_ring_size, alignment);
@@ -2963,7 +2963,7 @@ static bool si_update_spi_tmpring_size(struct si_context *sctx)
r600_resource_reference(&sctx->scratch_buffer, NULL);
sctx->scratch_buffer = (struct r600_resource*)
- r600_aligned_buffer_create(&sctx->screen->b.b,
+ si_aligned_buffer_create(&sctx->screen->b.b,
R600_RESOURCE_FLAG_UNMAPPABLE,
PIPE_USAGE_DEFAULT,
scratch_needed_size, 256);
@@ -3021,7 +3021,7 @@ static void si_init_tess_factor_ring(struct si_context *sctx)
/* Use 64K alignment for both rings, so that we can pass the address
* to shaders as one SGPR containing bits [16:47].
*/
- sctx->tf_ring = r600_aligned_buffer_create(sctx->b.b.screen,
+ sctx->tf_ring = si_aligned_buffer_create(sctx->b.b.screen,
R600_RESOURCE_FLAG_UNMAPPABLE,
PIPE_USAGE_DEFAULT,
32768 * sctx->screen->b.info.max_se,
@@ -3032,7 +3032,7 @@ static void si_init_tess_factor_ring(struct si_context *sctx)
assert(((sctx->tf_ring->width0 / 4) & C_030938_SIZE) == 0);
sctx->tess_offchip_ring =
- r600_aligned_buffer_create(sctx->b.b.screen,
+ si_aligned_buffer_create(sctx->b.b.screen,
R600_RESOURCE_FLAG_UNMAPPABLE,
PIPE_USAGE_DEFAULT,
max_offchip_buffers *
diff --git a/src/gallium/drivers/radeonsi/si_uvd.c b/src/gallium/drivers/radeonsi/si_uvd.c
index 2441ad248c6..4e8250664c1 100644
--- a/src/gallium/drivers/radeonsi/si_uvd.c
+++ b/src/gallium/drivers/radeonsi/si_uvd.c
@@ -98,7 +98,7 @@ struct pipe_video_buffer *si_video_buffer_create(struct pipe_context *pipe,
pbs[i] = &resources[i]->resource.buf;
}
- rvid_join_surfaces(&ctx->b, pbs, surfaces);
+ si_vid_join_surfaces(&ctx->b, pbs, surfaces);
for (i = 0; i < VL_NUM_COMPONENTS; ++i) {
if (!resources[i])
@@ -131,7 +131,7 @@ static struct pb_buffer* si_uvd_set_dtb(struct ruvd_msg *msg, struct vl_video_bu
msg->body.decode.dt_field_mode = buf->base.interlaced;
- ruvd_set_dt_surfaces(msg, &luma->surface, (chroma) ? &chroma->surface : NULL, type);
+ si_uvd_set_dt_surfaces(msg, &luma->surface, (chroma) ? &chroma->surface : NULL, type);
return luma->resource.buf;
}
@@ -160,8 +160,8 @@ struct pipe_video_codec *si_uvd_create_decoder(struct pipe_context *context,
bool vcn = (ctx->b.family == CHIP_RAVEN) ? true : false;
if (templ->entrypoint == PIPE_VIDEO_ENTRYPOINT_ENCODE)
- return rvce_create_encoder(context, templ, ctx->b.ws, si_vce_get_buffer);
+ return si_vce_create_encoder(context, templ, ctx->b.ws, si_vce_get_buffer);
return (vcn) ? radeon_create_decoder(context, templ) :
- ruvd_create_decoder(context, templ, si_uvd_set_dtb);
+ si_common_uvd_create_decoder(context, templ, si_uvd_set_dtb);
}
generated by cgit v1.2.3 (git 2.39.1) at 2024-12-02 06:22:03 +0000