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Diffstat (limited to 'src/gallium/drivers/radeonsi/si_descriptors.c')
-rw-r--r--src/gallium/drivers/radeonsi/si_descriptors.c63
1 files changed, 45 insertions, 18 deletions
diff --git a/src/gallium/drivers/radeonsi/si_descriptors.c b/src/gallium/drivers/radeonsi/si_descriptors.c
index 6b0ff91c2bc..bf2206dc1bc 100644
--- a/src/gallium/drivers/radeonsi/si_descriptors.c
+++ b/src/gallium/drivers/radeonsi/si_descriptors.c
@@ -129,7 +129,8 @@ static void si_init_descriptors(struct si_context *sctx,
PIPE_USAGE_DEFAULT,
SI_NUM_CONTEXTS * desc->context_size);
- r600_context_bo_reloc(&sctx->b, &sctx->b.rings.gfx, desc->buffer, RADEON_USAGE_READWRITE);
+ r600_context_bo_reloc(&sctx->b, &sctx->b.rings.gfx, desc->buffer,
+ RADEON_USAGE_READWRITE, RADEON_PRIO_SHADER_DATA);
va = r600_resource_va(sctx->b.b.screen, &desc->buffer->b.b);
/* We don't check for CS space here, because this should be called
@@ -301,6 +302,17 @@ static void si_release_sampler_views(struct si_sampler_views *views)
si_release_descriptors(&views->desc);
}
+static enum radeon_bo_priority si_get_resource_ro_priority(struct r600_resource *res)
+{
+ if (res->b.b.target == PIPE_BUFFER)
+ return RADEON_PRIO_SHADER_BUFFER_RO;
+
+ if (res->b.b.nr_samples > 1)
+ return RADEON_PRIO_SHADER_TEXTURE_MSAA;
+
+ return RADEON_PRIO_SHADER_TEXTURE_RO;
+}
+
static void si_sampler_views_begin_new_cs(struct si_context *sctx,
struct si_sampler_views *views)
{
@@ -312,10 +324,13 @@ static void si_sampler_views_begin_new_cs(struct si_context *sctx,
struct si_pipe_sampler_view *rview =
(struct si_pipe_sampler_view*)views->views[i];
- r600_context_bo_reloc(&sctx->b, &sctx->b.rings.gfx, rview->resource, RADEON_USAGE_READ);
+ r600_context_bo_reloc(&sctx->b, &sctx->b.rings.gfx,
+ rview->resource, RADEON_USAGE_READ,
+ si_get_resource_ro_priority(rview->resource));
}
- r600_context_bo_reloc(&sctx->b, &sctx->b.rings.gfx, views->desc.buffer, RADEON_USAGE_READWRITE);
+ r600_context_bo_reloc(&sctx->b, &sctx->b.rings.gfx, views->desc.buffer,
+ RADEON_USAGE_READWRITE, RADEON_PRIO_SHADER_DATA);
si_emit_shader_pointer(sctx, &views->desc);
}
@@ -333,7 +348,9 @@ void si_set_sampler_view(struct si_context *sctx, unsigned shader,
struct si_pipe_sampler_view *rview =
(struct si_pipe_sampler_view*)view;
- r600_context_bo_reloc(&sctx->b, &sctx->b.rings.gfx, rview->resource, RADEON_USAGE_READ);
+ r600_context_bo_reloc(&sctx->b, &sctx->b.rings.gfx,
+ rview->resource, RADEON_USAGE_READ,
+ si_get_resource_ro_priority(rview->resource));
pipe_sampler_view_reference(&views->views[slot], view);
views->desc_data[slot] = view_desc;
@@ -361,12 +378,14 @@ static void si_init_buffer_resources(struct si_context *sctx,
struct si_buffer_resources *buffers,
unsigned num_buffers, unsigned shader,
unsigned shader_userdata_index,
- enum radeon_bo_usage shader_usage)
+ enum radeon_bo_usage shader_usage,
+ enum radeon_bo_priority priority)
{
int i;
buffers->num_buffers = num_buffers;
buffers->shader_usage = shader_usage;
+ buffers->priority = priority;
buffers->buffers = CALLOC(num_buffers, sizeof(struct pipe_resource*));
buffers->desc_storage = CALLOC(num_buffers, sizeof(uint32_t) * 4);
@@ -408,11 +427,12 @@ static void si_buffer_resources_begin_new_cs(struct si_context *sctx,
r600_context_bo_reloc(&sctx->b, &sctx->b.rings.gfx,
(struct r600_resource*)buffers->buffers[i],
- buffers->shader_usage);
+ buffers->shader_usage, buffers->priority);
}
r600_context_bo_reloc(&sctx->b, &sctx->b.rings.gfx,
- buffers->desc.buffer, RADEON_USAGE_READWRITE);
+ buffers->desc.buffer, RADEON_USAGE_READWRITE,
+ RADEON_PRIO_SHADER_DATA);
si_emit_shader_pointer(sctx, &buffers->desc);
}
@@ -495,7 +515,8 @@ static void si_set_constant_buffer(struct pipe_context *ctx, uint shader, uint s
buffers->buffers[slot] = buffer;
r600_context_bo_reloc(&sctx->b, &sctx->b.rings.gfx,
- (struct r600_resource*)buffer, buffers->shader_usage);
+ (struct r600_resource*)buffer,
+ buffers->shader_usage, buffers->priority);
buffers->desc.enabled_mask |= 1 << slot;
} else {
/* Clear the descriptor. */
@@ -588,7 +609,7 @@ void si_set_ring_buffer(struct pipe_context *ctx, uint shader, uint slot,
pipe_resource_reference(&buffers->buffers[slot], input->buffer);
r600_context_bo_reloc(&sctx->b, &sctx->b.rings.gfx,
(struct r600_resource*)input->buffer,
- buffers->shader_usage);
+ buffers->shader_usage, buffers->priority);
buffers->desc.enabled_mask |= 1 << slot;
} else {
/* Clear the descriptor. */
@@ -643,7 +664,7 @@ static void si_set_streamout_targets(struct pipe_context *ctx,
buffer);
r600_context_bo_reloc(&sctx->b, &sctx->b.rings.gfx,
(struct r600_resource*)buffer,
- buffers->shader_usage);
+ buffers->shader_usage, buffers->priority);
buffers->desc.enabled_mask |= 1 << bufidx;
} else {
/* Clear the descriptor and unset the resource. */
@@ -731,7 +752,8 @@ static void si_invalidate_buffer(struct pipe_context *ctx, struct pipe_resource
old_va, buf);
r600_context_bo_reloc(&sctx->b, &sctx->b.rings.gfx,
- rbuffer, buffers->shader_usage);
+ rbuffer, buffers->shader_usage,
+ buffers->priority);
buffers->desc.dirty_mask |= 1 << i;
found = true;
@@ -765,7 +787,8 @@ static void si_invalidate_buffer(struct pipe_context *ctx, struct pipe_resource
old_va, buf);
r600_context_bo_reloc(&sctx->b, &sctx->b.rings.gfx,
- rbuffer, buffers->shader_usage);
+ rbuffer, buffers->shader_usage,
+ buffers->priority);
buffers->desc.dirty_mask |= 1 << i;
found = true;
@@ -790,7 +813,8 @@ static void si_invalidate_buffer(struct pipe_context *ctx, struct pipe_resource
old_va, buf);
r600_context_bo_reloc(&sctx->b, &sctx->b.rings.gfx,
- rbuffer, RADEON_USAGE_READ);
+ rbuffer, RADEON_USAGE_READ,
+ RADEON_PRIO_SHADER_BUFFER_RO);
views->desc.dirty_mask |= 1 << i;
found = true;
@@ -853,7 +877,8 @@ static void si_clear_buffer(struct pipe_context *ctx, struct pipe_resource *dst,
/* This must be done after need_cs_space. */
r600_context_bo_reloc(&sctx->b, &sctx->b.rings.gfx,
- (struct r600_resource*)dst, RADEON_USAGE_WRITE);
+ (struct r600_resource*)dst, RADEON_USAGE_WRITE,
+ RADEON_PRIO_MIN);
/* Flush the caches for the first copy only.
* Also wait for the previous CP DMA operations. */
@@ -927,8 +952,10 @@ void si_copy_buffer(struct si_context *sctx,
}
/* This must be done after r600_need_cs_space. */
- r600_context_bo_reloc(&sctx->b, &sctx->b.rings.gfx, (struct r600_resource*)src, RADEON_USAGE_READ);
- r600_context_bo_reloc(&sctx->b, &sctx->b.rings.gfx, (struct r600_resource*)dst, RADEON_USAGE_WRITE);
+ r600_context_bo_reloc(&sctx->b, &sctx->b.rings.gfx, (struct r600_resource*)src,
+ RADEON_USAGE_READ, RADEON_PRIO_MIN);
+ r600_context_bo_reloc(&sctx->b, &sctx->b.rings.gfx, (struct r600_resource*)dst,
+ RADEON_USAGE_WRITE, RADEON_PRIO_MIN);
si_emit_cp_dma_copy_buffer(sctx, dst_offset, src_offset, byte_count, sync_flags);
@@ -954,12 +981,12 @@ void si_init_all_descriptors(struct si_context *sctx)
for (i = 0; i < SI_NUM_SHADERS; i++) {
si_init_buffer_resources(sctx, &sctx->const_buffers[i],
NUM_CONST_BUFFERS, i, SI_SGPR_CONST,
- RADEON_USAGE_READ);
+ RADEON_USAGE_READ, RADEON_PRIO_SHADER_BUFFER_RO);
si_init_buffer_resources(sctx, &sctx->rw_buffers[i],
i == PIPE_SHADER_VERTEX ?
SI_RW_SO + 4 : SI_RW_SO,
i, SI_SGPR_RW_BUFFERS,
- RADEON_USAGE_READWRITE);
+ RADEON_USAGE_READWRITE, RADEON_PRIO_SHADER_RESOURCE_RW);
si_init_sampler_views(sctx, &sctx->samplers[i].views, i);
generated by cgit v1.2.3 (git 2.39.1) at 2024-12-13 16:01:49 +0000