1 files changed, 23 insertions, 46 deletions

diff --git a/src/gallium/drivers/r600/r600_hw_context.c b/src/gallium/drivers/r600/r600_hw_context.c
index ec098c1f7cf..78b5b293060 100644
--- a/src/gallium/drivers/r600/r600_hw_context.c
+++ b/src/gallium/drivers/r600/r600_hw_context.c
@@ -404,7 +404,9 @@ void r600_need_cs_space(struct r600_context *ctx, unsigned num_dw,
 	num_dw += ctx->num_cs_dw_nontimer_queries_suspend;
 
 	/* Count in streamout_end at the end of CS. */
-	num_dw += ctx->num_cs_dw_streamout_end;
+	if (ctx->streamout.begin_emitted) {
+		num_dw += ctx->streamout.num_dw_for_end;
+	}
 
 	/* Count in render_condition(NULL) at the end of CS. */
 	if (ctx->predicate_drawing) {
@@ -727,7 +729,7 @@ void r600_context_flush(struct r600_context *ctx, unsigned flags)
 		return;
 
 	ctx->nontimer_queries_suspended = false;
-	ctx->streamout_suspended = false;
+	ctx->streamout.suspended = false;
 
 	/* suspend queries */
 	if (ctx->num_cs_dw_nontimer_queries_suspend) {
@@ -735,9 +737,9 @@ void r600_context_flush(struct r600_context *ctx, unsigned flags)
 		ctx->nontimer_queries_suspended = true;
 	}
 
-	if (ctx->num_cs_dw_streamout_end) {
-		r600_context_streamout_end(ctx);
-		ctx->streamout_suspended = true;
+	if (ctx->streamout.begin_emitted) {
+		r600_emit_streamout_end(ctx);
+		ctx->streamout.suspended = true;
 	}
 
 	/* flush is needed to avoid lockups on some chips with user fences
@@ -854,9 +856,9 @@ void r600_begin_new_cs(struct r600_context *ctx)
 		r600_sampler_states_dirty(ctx, &samplers->states);
 	}
 
-	if (ctx->streamout_suspended) {
-		ctx->streamout_start = TRUE;
-		ctx->streamout_append_bitmask = ~0;
+	if (ctx->streamout.suspended) {
+		ctx->streamout.append_bitmask = ctx->streamout.enabled_mask;
+		r600_streamout_buffers_dirty(ctx);
 	}
 
 	/* resume queries */
@@ -940,48 +942,23 @@ static void r600_set_streamout_enable(struct r600_context *ctx, unsigned buffer_
 	}
 }
 
-void r600_context_streamout_begin(struct r600_context *ctx)
+void r600_emit_streamout_begin(struct r600_context *ctx, struct r600_atom *atom)
 {
 	struct radeon_winsys_cs *cs = ctx->rings.gfx.cs;
-	struct r600_so_target **t = ctx->so_targets;
+	struct r600_so_target **t = ctx->streamout.targets;
 	unsigned *stride_in_dw = ctx->vs_shader->so.stride;
-	unsigned buffer_en, i, update_flags = 0;
+	unsigned i, update_flags = 0;
 	uint64_t va;
-	unsigned num_cs_dw_streamout_end;
-
-	buffer_en = (ctx->num_so_targets >= 1 && t[0] ? 1 : 0) |
-		    (ctx->num_so_targets >= 2 && t[1] ? 2 : 0) |
-		    (ctx->num_so_targets >= 3 && t[2] ? 4 : 0) |
-		    (ctx->num_so_targets >= 4 && t[3] ? 8 : 0);
-
-	num_cs_dw_streamout_end =
-		12 + /* flush_vgt_streamout */
-		util_bitcount(buffer_en) * 8 + /* STRMOUT_BUFFER_UPDATE */
-		3 /* set_streamout_enable(0) */;
-
-	r600_need_cs_space(ctx,
-			   12 + /* flush_vgt_streamout */
-			   6 + /* set_streamout_enable */
-			   util_bitcount(buffer_en) * 7 + /* SET_CONTEXT_REG */
-			   (ctx->family >= CHIP_RS780 &&
-			    ctx->family <= CHIP_RV740 ? util_bitcount(buffer_en) * 5 : 0) + /* STRMOUT_BASE_UPDATE */
-			   util_bitcount(buffer_en & ctx->streamout_append_bitmask) * 8 + /* STRMOUT_BUFFER_UPDATE */
-			   util_bitcount(buffer_en & ~ctx->streamout_append_bitmask) * 6 + /* STRMOUT_BUFFER_UPDATE */
-			   (ctx->family > CHIP_R600 && ctx->family < CHIP_RS780 ? 2 : 0) + /* SURFACE_BASE_UPDATE */
-			   num_cs_dw_streamout_end, TRUE);
-
-	/* This must be set after r600_need_cs_space. */
-	ctx->num_cs_dw_streamout_end = num_cs_dw_streamout_end;
 
 	if (ctx->chip_class >= EVERGREEN) {
 		evergreen_flush_vgt_streamout(ctx);
-		evergreen_set_streamout_enable(ctx, buffer_en);
+		evergreen_set_streamout_enable(ctx, ctx->streamout.enabled_mask);
 	} else {
 		r600_flush_vgt_streamout(ctx);
-		r600_set_streamout_enable(ctx, buffer_en);
+		r600_set_streamout_enable(ctx, ctx->streamout.enabled_mask);
 	}
 
-	for (i = 0; i < ctx->num_so_targets; i++) {
+	for (i = 0; i < ctx->streamout.num_targets; i++) {
 		if (t[i]) {
 			t[i]->stride_in_dw = stride_in_dw[i];
 			t[i]->so_index = i;
@@ -1014,7 +991,7 @@ void r600_context_streamout_begin(struct r600_context *ctx)
 							      RADEON_USAGE_WRITE);
 			}
 
-			if (ctx->streamout_append_bitmask & (1 << i)) {
+			if (ctx->streamout.append_bitmask & (1 << i)) {
 				va = r600_resource_va(&ctx->screen->screen,
 						      (void*)t[i]->buf_filled_size) + t[i]->buf_filled_size_offset;
 				/* Append. */
@@ -1043,16 +1020,17 @@ void r600_context_streamout_begin(struct r600_context *ctx)
 		}
 	}
 
-	if (ctx->family > CHIP_R600 && ctx->family < CHIP_RS780) {
+	if (ctx->family > CHIP_R600 && ctx->family < CHIP_RV770) {
 		cs->buf[cs->cdw++] = PKT3(PKT3_SURFACE_BASE_UPDATE, 0, 0);
 		cs->buf[cs->cdw++] = update_flags;
 	}
+	ctx->streamout.begin_emitted = true;
 }
 
-void r600_context_streamout_end(struct r600_context *ctx)
+void r600_emit_streamout_end(struct r600_context *ctx)
 {
 	struct radeon_winsys_cs *cs = ctx->rings.gfx.cs;
-	struct r600_so_target **t = ctx->so_targets;
+	struct r600_so_target **t = ctx->streamout.targets;
 	unsigned i;
 	uint64_t va;
 
@@ -1062,7 +1040,7 @@ void r600_context_streamout_end(struct r600_context *ctx)
 		r600_flush_vgt_streamout(ctx);
 	}
 
-	for (i = 0; i < ctx->num_so_targets; i++) {
+	for (i = 0; i < ctx->streamout.num_targets; i++) {
 		if (t[i]) {
 			va = r600_resource_va(&ctx->screen->screen,
 					      (void*)t[i]->buf_filled_size) + t[i]->buf_filled_size_offset;
@@ -1079,7 +1057,6 @@ void r600_context_streamout_end(struct r600_context *ctx)
 			cs->buf[cs->cdw++] =
 				r600_context_bo_reloc(ctx,  &ctx->rings.gfx, t[i]->buf_filled_size,
 						      RADEON_USAGE_WRITE);
-
 		}
 	}
 
@@ -1093,7 +1070,7 @@ void r600_context_streamout_end(struct r600_context *ctx)
 		r600_set_streamout_enable(ctx, 0);
 	}
 	ctx->flags |= R600_CONTEXT_WAIT_3D_IDLE | R600_CONTEXT_FLUSH_AND_INV;
-	ctx->num_cs_dw_streamout_end = 0;
+	ctx->streamout.begin_emitted = false;
 }
 
 /* The max number of bytes to copy per packet. */