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-rw-r--r--src/gallium/drivers/freedreno/a3xx/fd3_context.c4
-rw-r--r--src/gallium/drivers/freedreno/a3xx/fd3_context.h5
-rw-r--r--src/gallium/drivers/freedreno/a3xx/fd3_draw.c15
-rw-r--r--src/gallium/drivers/freedreno/a3xx/fd3_emit.c15
-rw-r--r--src/gallium/drivers/freedreno/a3xx/fd3_gmem.c145
5 files changed, 90 insertions, 94 deletions
diff --git a/src/gallium/drivers/freedreno/a3xx/fd3_context.c b/src/gallium/drivers/freedreno/a3xx/fd3_context.c
index e47bbff5643..2ffc2e0e53a 100644
--- a/src/gallium/drivers/freedreno/a3xx/fd3_context.c
+++ b/src/gallium/drivers/freedreno/a3xx/fd3_context.c
@@ -43,8 +43,6 @@ fd3_context_destroy(struct pipe_context *pctx)
{
struct fd3_context *fd3_ctx = fd3_context(fd_context(pctx));
- util_dynarray_fini(&fd3_ctx->rbrc_patches);
-
fd_bo_del(fd3_ctx->vs_pvt_mem);
fd_bo_del(fd3_ctx->fs_pvt_mem);
fd_bo_del(fd3_ctx->vsc_size_mem);
@@ -127,8 +125,6 @@ fd3_context_create(struct pipe_screen *pscreen, void *priv, unsigned flags)
if (!pctx)
return NULL;
- util_dynarray_init(&fd3_ctx->rbrc_patches);
-
fd3_ctx->vs_pvt_mem = fd_bo_new(screen->dev, 0x2000,
DRM_FREEDRENO_GEM_TYPE_KMEM);
diff --git a/src/gallium/drivers/freedreno/a3xx/fd3_context.h b/src/gallium/drivers/freedreno/a3xx/fd3_context.h
index b4c2ebe570c..07354110361 100644
--- a/src/gallium/drivers/freedreno/a3xx/fd3_context.h
+++ b/src/gallium/drivers/freedreno/a3xx/fd3_context.h
@@ -41,11 +41,6 @@
struct fd3_context {
struct fd_context base;
- /* Keep track of writes to RB_RENDER_CONTROL which need to be patched
- * once we know whether or not to use GMEM, and GMEM tile pitch.
- */
- struct util_dynarray rbrc_patches;
-
struct fd_bo *vs_pvt_mem, *fs_pvt_mem;
/* This only needs to be 4 * num_of_pipes bytes (ie. 32 bytes). We
diff --git a/src/gallium/drivers/freedreno/a3xx/fd3_draw.c b/src/gallium/drivers/freedreno/a3xx/fd3_draw.c
index 0593b253f1a..34d782b95ce 100644
--- a/src/gallium/drivers/freedreno/a3xx/fd3_draw.c
+++ b/src/gallium/drivers/freedreno/a3xx/fd3_draw.c
@@ -84,8 +84,7 @@ draw_impl(struct fd_context *ctx, struct fd_ringbuffer *ring,
(info->mode == PIPE_PRIM_POINTS))
primtype = DI_PT_POINTLIST_PSIZE;
- fd_draw_emit(ctx, ring,
- primtype,
+ fd_draw_emit(ctx->batch, ring, primtype,
emit->key.binning_pass ? IGNORE_VISIBILITY : USE_VISIBILITY,
info);
}
@@ -223,7 +222,7 @@ fd3_clear_binning(struct fd_context *ctx, unsigned dirty)
fd3_emit_state(ctx, ring, &emit);
fd3_emit_vertex_bufs(ring, &emit);
- reset_viewport(ring, &ctx->framebuffer);
+ reset_viewport(ring, &ctx->batch->framebuffer);
OUT_PKT0(ring, REG_A3XX_PC_PRIM_VTX_CNTL, 1);
OUT_RING(ring, A3XX_PC_PRIM_VTX_CNTL_STRIDE_IN_VPC(0) |
@@ -240,7 +239,7 @@ fd3_clear_binning(struct fd_context *ctx, unsigned dirty)
fd_event_write(ctx, ring, PERFCOUNTER_STOP);
- fd_draw(ctx, ring, DI_PT_RECTLIST, IGNORE_VISIBILITY,
+ fd_draw(ctx->batch, ring, DI_PT_RECTLIST, IGNORE_VISIBILITY,
DI_SRC_SEL_AUTO_INDEX, 2, 0, INDEX_SIZE_IGN, 0, 0, NULL);
}
@@ -249,7 +248,7 @@ fd3_clear(struct fd_context *ctx, unsigned buffers,
const union pipe_color_union *color, double depth, unsigned stencil)
{
struct fd3_context *fd3_ctx = fd3_context(ctx);
- struct pipe_framebuffer_state *pfb = &ctx->framebuffer;
+ struct pipe_framebuffer_state *pfb = &ctx->batch->framebuffer;
struct fd_ringbuffer *ring = ctx->batch->draw;
unsigned dirty = ctx->dirty;
unsigned i;
@@ -270,7 +269,7 @@ fd3_clear(struct fd_context *ctx, unsigned buffers,
/* emit generic state now: */
fd3_emit_state(ctx, ring, &emit);
- reset_viewport(ring, &ctx->framebuffer);
+ reset_viewport(ring, &ctx->batch->framebuffer);
OUT_PKT0(ring, REG_A3XX_RB_BLEND_ALPHA, 1);
OUT_RING(ring, A3XX_RB_BLEND_ALPHA_UINT(0xff) |
@@ -278,7 +277,7 @@ fd3_clear(struct fd_context *ctx, unsigned buffers,
OUT_PKT0(ring, REG_A3XX_RB_RENDER_CONTROL, 1);
OUT_RINGP(ring, A3XX_RB_RENDER_CONTROL_ALPHA_TEST_FUNC(FUNC_NEVER),
- &fd3_ctx->rbrc_patches);
+ &ctx->batch->rbrc_patches);
if (buffers & PIPE_CLEAR_DEPTH) {
OUT_PKT0(ring, REG_A3XX_RB_DEPTH_CONTROL, 1);
@@ -374,7 +373,7 @@ fd3_clear(struct fd_context *ctx, unsigned buffers,
fd_event_write(ctx, ring, PERFCOUNTER_STOP);
- fd_draw(ctx, ring, DI_PT_RECTLIST, USE_VISIBILITY,
+ fd_draw(ctx->batch, ring, DI_PT_RECTLIST, USE_VISIBILITY,
DI_SRC_SEL_AUTO_INDEX, 2, 0, INDEX_SIZE_IGN, 0, 0, NULL);
}
diff --git a/src/gallium/drivers/freedreno/a3xx/fd3_emit.c b/src/gallium/drivers/freedreno/a3xx/fd3_emit.c
index 45185edb505..eef5b52f12c 100644
--- a/src/gallium/drivers/freedreno/a3xx/fd3_emit.c
+++ b/src/gallium/drivers/freedreno/a3xx/fd3_emit.c
@@ -516,7 +516,7 @@ fd3_emit_state(struct fd_context *ctx, struct fd_ringbuffer *ring,
*/
OUT_PKT0(ring, REG_A3XX_RB_RENDER_CONTROL, 1);
- OUT_RINGP(ring, val, &fd3_context(ctx)->rbrc_patches);
+ OUT_RINGP(ring, val, &ctx->batch->rbrc_patches);
}
if (dirty & (FD_DIRTY_ZSA | FD_DIRTY_STENCIL_REF)) {
@@ -631,10 +631,10 @@ fd3_emit_state(struct fd_context *ctx, struct fd_ringbuffer *ring,
OUT_RING(ring, A3XX_GRAS_SC_WINDOW_SCISSOR_BR_X(scissor->maxx - 1) |
A3XX_GRAS_SC_WINDOW_SCISSOR_BR_Y(scissor->maxy - 1));
- ctx->max_scissor.minx = MIN2(ctx->max_scissor.minx, scissor->minx);
- ctx->max_scissor.miny = MIN2(ctx->max_scissor.miny, scissor->miny);
- ctx->max_scissor.maxx = MAX2(ctx->max_scissor.maxx, scissor->maxx);
- ctx->max_scissor.maxy = MAX2(ctx->max_scissor.maxy, scissor->maxy);
+ ctx->batch->max_scissor.minx = MIN2(ctx->batch->max_scissor.minx, scissor->minx);
+ ctx->batch->max_scissor.miny = MIN2(ctx->batch->max_scissor.miny, scissor->miny);
+ ctx->batch->max_scissor.maxx = MAX2(ctx->batch->max_scissor.maxx, scissor->maxx);
+ ctx->batch->max_scissor.maxy = MAX2(ctx->batch->max_scissor.maxy, scissor->maxy);
}
if (dirty & FD_DIRTY_VIEWPORT) {
@@ -649,7 +649,7 @@ fd3_emit_state(struct fd_context *ctx, struct fd_ringbuffer *ring,
}
if (dirty & (FD_DIRTY_PROG | FD_DIRTY_FRAMEBUFFER | FD_DIRTY_BLEND_DUAL)) {
- struct pipe_framebuffer_state *pfb = &ctx->framebuffer;
+ struct pipe_framebuffer_state *pfb = &ctx->batch->framebuffer;
int nr_cbufs = pfb->nr_cbufs;
if (fd3_blend_stateobj(ctx->blend)->rb_render_control &
A3XX_RB_RENDER_CONTROL_DUAL_COLOR_IN_ENABLE)
@@ -673,7 +673,8 @@ fd3_emit_state(struct fd_context *ctx, struct fd_ringbuffer *ring,
uint32_t i;
for (i = 0; i < ARRAY_SIZE(blend->rb_mrt); i++) {
- enum pipe_format format = pipe_surface_format(ctx->framebuffer.cbufs[i]);
+ enum pipe_format format =
+ pipe_surface_format(ctx->batch->framebuffer.cbufs[i]);
const struct util_format_description *desc =
util_format_description(format);
bool is_float = util_format_is_float(format);
diff --git a/src/gallium/drivers/freedreno/a3xx/fd3_gmem.c b/src/gallium/drivers/freedreno/a3xx/fd3_gmem.c
index 2449a84c721..b9af45683f9 100644
--- a/src/gallium/drivers/freedreno/a3xx/fd3_gmem.c
+++ b/src/gallium/drivers/freedreno/a3xx/fd3_gmem.c
@@ -128,9 +128,9 @@ emit_mrt(struct fd_ringbuffer *ring, unsigned nr_bufs,
}
static bool
-use_hw_binning(struct fd_context *ctx)
+use_hw_binning(struct fd_batch *batch)
{
- struct fd_gmem_stateobj *gmem = &ctx->gmem;
+ struct fd_gmem_stateobj *gmem = &batch->ctx->gmem;
/* workaround: combining scissor optimization and hw binning
* seems problematic. Seems like we end up with a mismatch
@@ -153,13 +153,14 @@ use_hw_binning(struct fd_context *ctx)
}
/* workaround for (hlsq?) lockup with hw binning on a3xx patchlevel 0 */
-static void update_vsc_pipe(struct fd_context *ctx);
+static void update_vsc_pipe(struct fd_batch *batch);
static void
-emit_binning_workaround(struct fd_context *ctx)
+emit_binning_workaround(struct fd_batch *batch)
{
+ struct fd_context *ctx = batch->ctx;
struct fd3_context *fd3_ctx = fd3_context(ctx);
struct fd_gmem_stateobj *gmem = &ctx->gmem;
- struct fd_ringbuffer *ring = ctx->ring;
+ struct fd_ringbuffer *ring = batch->gmem;
struct fd3_emit emit = {
.debug = &ctx->debug,
.vtx = &fd3_ctx->solid_vbuf_state,
@@ -308,12 +309,12 @@ emit_binning_workaround(struct fd_context *ctx)
/* transfer from gmem to system memory (ie. normal RAM) */
static void
-emit_gmem2mem_surf(struct fd_context *ctx,
+emit_gmem2mem_surf(struct fd_batch *batch,
enum adreno_rb_copy_control_mode mode,
bool stencil,
uint32_t base, struct pipe_surface *psurf)
{
- struct fd_ringbuffer *ring = ctx->ring;
+ struct fd_ringbuffer *ring = batch->gmem;
struct fd_resource *rsc = fd_resource(psurf->texture);
enum pipe_format format = psurf->format;
if (stencil) {
@@ -342,16 +343,17 @@ emit_gmem2mem_surf(struct fd_context *ctx,
A3XX_RB_COPY_DEST_INFO_ENDIAN(ENDIAN_NONE) |
A3XX_RB_COPY_DEST_INFO_SWAP(fd3_pipe2swap(format)));
- fd_draw(ctx, ring, DI_PT_RECTLIST, IGNORE_VISIBILITY,
+ fd_draw(batch, ring, DI_PT_RECTLIST, IGNORE_VISIBILITY,
DI_SRC_SEL_AUTO_INDEX, 2, 0, INDEX_SIZE_IGN, 0, 0, NULL);
}
static void
-fd3_emit_tile_gmem2mem(struct fd_context *ctx, struct fd_tile *tile)
+fd3_emit_tile_gmem2mem(struct fd_batch *batch, struct fd_tile *tile)
{
+ struct fd_context *ctx = batch->ctx;
struct fd3_context *fd3_ctx = fd3_context(ctx);
- struct fd_ringbuffer *ring = ctx->ring;
- struct pipe_framebuffer_state *pfb = &ctx->framebuffer;
+ struct fd_ringbuffer *ring = batch->gmem;
+ struct pipe_framebuffer_state *pfb = &batch->framebuffer;
struct fd3_emit emit = {
.debug = &ctx->debug,
.vtx = &fd3_ctx->solid_vbuf_state,
@@ -437,23 +439,23 @@ fd3_emit_tile_gmem2mem(struct fd_context *ctx, struct fd_tile *tile)
fd3_program_emit(ring, &emit, 0, NULL);
fd3_emit_vertex_bufs(ring, &emit);
- if (ctx->resolve & (FD_BUFFER_DEPTH | FD_BUFFER_STENCIL)) {
+ if (batch->resolve & (FD_BUFFER_DEPTH | FD_BUFFER_STENCIL)) {
struct fd_resource *rsc = fd_resource(pfb->zsbuf->texture);
- if (!rsc->stencil || ctx->resolve & FD_BUFFER_DEPTH)
- emit_gmem2mem_surf(ctx, RB_COPY_DEPTH_STENCIL, false,
+ if (!rsc->stencil || batch->resolve & FD_BUFFER_DEPTH)
+ emit_gmem2mem_surf(batch, RB_COPY_DEPTH_STENCIL, false,
ctx->gmem.zsbuf_base[0], pfb->zsbuf);
- if (rsc->stencil && ctx->resolve & FD_BUFFER_STENCIL)
- emit_gmem2mem_surf(ctx, RB_COPY_DEPTH_STENCIL, true,
+ if (rsc->stencil && batch->resolve & FD_BUFFER_STENCIL)
+ emit_gmem2mem_surf(batch, RB_COPY_DEPTH_STENCIL, true,
ctx->gmem.zsbuf_base[1], pfb->zsbuf);
}
- if (ctx->resolve & FD_BUFFER_COLOR) {
+ if (batch->resolve & FD_BUFFER_COLOR) {
for (i = 0; i < pfb->nr_cbufs; i++) {
if (!pfb->cbufs[i])
continue;
- if (!(ctx->resolve & (PIPE_CLEAR_COLOR0 << i)))
+ if (!(batch->resolve & (PIPE_CLEAR_COLOR0 << i)))
continue;
- emit_gmem2mem_surf(ctx, RB_COPY_RESOLVE, false,
+ emit_gmem2mem_surf(batch, RB_COPY_RESOLVE, false,
ctx->gmem.cbuf_base[i], pfb->cbufs[i]);
}
}
@@ -472,10 +474,10 @@ fd3_emit_tile_gmem2mem(struct fd_context *ctx, struct fd_tile *tile)
/* transfer from system memory to gmem */
static void
-emit_mem2gmem_surf(struct fd_context *ctx, uint32_t bases[],
+emit_mem2gmem_surf(struct fd_batch *batch, uint32_t bases[],
struct pipe_surface **psurf, uint32_t bufs, uint32_t bin_w)
{
- struct fd_ringbuffer *ring = ctx->ring;
+ struct fd_ringbuffer *ring = batch->gmem;
struct pipe_surface *zsbufs[2];
assert(bufs > 0);
@@ -502,7 +504,7 @@ emit_mem2gmem_surf(struct fd_context *ctx, uint32_t bases[],
OUT_PKT0(ring, REG_A3XX_RB_DEPTH_INFO, 2);
OUT_RING(ring, A3XX_RB_DEPTH_INFO_DEPTH_BASE(bases[0]) |
A3XX_RB_DEPTH_INFO_DEPTH_FORMAT(DEPTHX_32));
- OUT_RING(ring, A3XX_RB_DEPTH_PITCH(4 * ctx->gmem.bin_w));
+ OUT_RING(ring, A3XX_RB_DEPTH_PITCH(4 * batch->ctx->gmem.bin_w));
if (psurf[0]->format == PIPE_FORMAT_Z32_FLOAT) {
OUT_PKT0(ring, REG_A3XX_RB_MRT_CONTROL(0), 1);
@@ -523,17 +525,18 @@ emit_mem2gmem_surf(struct fd_context *ctx, uint32_t bases[],
fd3_emit_gmem_restore_tex(ring, psurf, bufs);
- fd_draw(ctx, ring, DI_PT_RECTLIST, IGNORE_VISIBILITY,
+ fd_draw(batch, ring, DI_PT_RECTLIST, IGNORE_VISIBILITY,
DI_SRC_SEL_AUTO_INDEX, 2, 0, INDEX_SIZE_IGN, 0, 0, NULL);
}
static void
-fd3_emit_tile_mem2gmem(struct fd_context *ctx, struct fd_tile *tile)
+fd3_emit_tile_mem2gmem(struct fd_batch *batch, struct fd_tile *tile)
{
+ struct fd_context *ctx = batch->ctx;
struct fd3_context *fd3_ctx = fd3_context(ctx);
struct fd_gmem_stateobj *gmem = &ctx->gmem;
- struct fd_ringbuffer *ring = ctx->ring;
- struct pipe_framebuffer_state *pfb = &ctx->framebuffer;
+ struct fd_ringbuffer *ring = batch->gmem;
+ struct pipe_framebuffer_state *pfb = &batch->framebuffer;
struct fd3_emit emit = {
.debug = &ctx->debug,
.vtx = &fd3_ctx->blit_vbuf_state,
@@ -655,14 +658,14 @@ fd3_emit_tile_mem2gmem(struct fd_context *ctx, struct fd_tile *tile)
bin_w = gmem->bin_w;
bin_h = gmem->bin_h;
- if (fd_gmem_needs_restore(ctx, tile, FD_BUFFER_COLOR)) {
+ if (fd_gmem_needs_restore(batch, tile, FD_BUFFER_COLOR)) {
emit.prog = &ctx->blit_prog[pfb->nr_cbufs - 1];
emit.fp = NULL; /* frag shader changed so clear cache */
fd3_program_emit(ring, &emit, pfb->nr_cbufs, pfb->cbufs);
- emit_mem2gmem_surf(ctx, gmem->cbuf_base, pfb->cbufs, pfb->nr_cbufs, bin_w);
+ emit_mem2gmem_surf(batch, gmem->cbuf_base, pfb->cbufs, pfb->nr_cbufs, bin_w);
}
- if (fd_gmem_needs_restore(ctx, tile, FD_BUFFER_DEPTH | FD_BUFFER_STENCIL)) {
+ if (fd_gmem_needs_restore(batch, tile, FD_BUFFER_DEPTH | FD_BUFFER_STENCIL)) {
if (pfb->zsbuf->format != PIPE_FORMAT_Z32_FLOAT_S8X24_UINT &&
pfb->zsbuf->format != PIPE_FORMAT_Z32_FLOAT) {
/* Non-float can use a regular color write. It's split over 8-bit
@@ -680,7 +683,7 @@ fd3_emit_tile_mem2gmem(struct fd_context *ctx, struct fd_tile *tile)
}
emit.fp = NULL; /* frag shader changed so clear cache */
fd3_program_emit(ring, &emit, 1, &pfb->zsbuf);
- emit_mem2gmem_surf(ctx, gmem->zsbuf_base, &pfb->zsbuf, 1, bin_w);
+ emit_mem2gmem_surf(batch, gmem->zsbuf_base, &pfb->zsbuf, 1, bin_w);
}
OUT_PKT0(ring, REG_A3XX_GRAS_SC_CONTROL, 1);
@@ -695,34 +698,33 @@ fd3_emit_tile_mem2gmem(struct fd_context *ctx, struct fd_tile *tile)
}
static void
-patch_draws(struct fd_context *ctx, enum pc_di_vis_cull_mode vismode)
+patch_draws(struct fd_batch *batch, enum pc_di_vis_cull_mode vismode)
{
unsigned i;
- for (i = 0; i < fd_patch_num_elements(&ctx->draw_patches); i++) {
- struct fd_cs_patch *patch = fd_patch_element(&ctx->draw_patches, i);
+ for (i = 0; i < fd_patch_num_elements(&batch->draw_patches); i++) {
+ struct fd_cs_patch *patch = fd_patch_element(&batch->draw_patches, i);
*patch->cs = patch->val | DRAW(0, 0, 0, vismode, 0);
}
- util_dynarray_resize(&ctx->draw_patches, 0);
+ util_dynarray_resize(&batch->draw_patches, 0);
}
static void
-patch_rbrc(struct fd_context *ctx, uint32_t val)
+patch_rbrc(struct fd_batch *batch, uint32_t val)
{
- struct fd3_context *fd3_ctx = fd3_context(ctx);
unsigned i;
- for (i = 0; i < fd_patch_num_elements(&fd3_ctx->rbrc_patches); i++) {
- struct fd_cs_patch *patch = fd_patch_element(&fd3_ctx->rbrc_patches, i);
+ for (i = 0; i < fd_patch_num_elements(&batch->rbrc_patches); i++) {
+ struct fd_cs_patch *patch = fd_patch_element(&batch->rbrc_patches, i);
*patch->cs = patch->val | val;
}
- util_dynarray_resize(&fd3_ctx->rbrc_patches, 0);
+ util_dynarray_resize(&batch->rbrc_patches, 0);
}
/* for rendering directly to system memory: */
static void
-fd3_emit_sysmem_prep(struct fd_context *ctx)
+fd3_emit_sysmem_prep(struct fd_batch *batch)
{
- struct pipe_framebuffer_state *pfb = &ctx->framebuffer;
- struct fd_ringbuffer *ring = ctx->ring;
+ struct pipe_framebuffer_state *pfb = &batch->framebuffer;
+ struct fd_ringbuffer *ring = batch->gmem;
uint32_t i, pitch = 0;
for (i = 0; i < pfb->nr_cbufs; i++) {
@@ -732,7 +734,7 @@ fd3_emit_sysmem_prep(struct fd_context *ctx)
pitch = fd_resource(psurf->texture)->slices[psurf->u.tex.level].pitch;
}
- fd3_emit_restore(ctx, ring);
+ fd3_emit_restore(batch->ctx, ring);
OUT_PKT0(ring, REG_A3XX_RB_FRAME_BUFFER_DIMENSION, 1);
OUT_RING(ring, A3XX_RB_FRAME_BUFFER_DIMENSION_WIDTH(pfb->width) |
@@ -757,15 +759,16 @@ fd3_emit_sysmem_prep(struct fd_context *ctx)
A3XX_RB_MODE_CONTROL_MARB_CACHE_SPLIT_MODE |
A3XX_RB_MODE_CONTROL_MRT(MAX2(1, pfb->nr_cbufs) - 1));
- patch_draws(ctx, IGNORE_VISIBILITY);
- patch_rbrc(ctx, A3XX_RB_RENDER_CONTROL_BIN_WIDTH(pitch));
+ patch_draws(batch, IGNORE_VISIBILITY);
+ patch_rbrc(batch, A3XX_RB_RENDER_CONTROL_BIN_WIDTH(pitch));
}
static void
-update_vsc_pipe(struct fd_context *ctx)
+update_vsc_pipe(struct fd_batch *batch)
{
+ struct fd_context *ctx = batch->ctx;
struct fd3_context *fd3_ctx = fd3_context(ctx);
- struct fd_ringbuffer *ring = ctx->ring;
+ struct fd_ringbuffer *ring = batch->gmem;
int i;
OUT_PKT0(ring, REG_A3XX_VSC_SIZE_ADDRESS, 1);
@@ -790,12 +793,12 @@ update_vsc_pipe(struct fd_context *ctx)
}
static void
-emit_binning_pass(struct fd_context *ctx)
+emit_binning_pass(struct fd_batch *batch)
{
+ struct fd_context *ctx = batch->ctx;
struct fd_gmem_stateobj *gmem = &ctx->gmem;
- struct pipe_framebuffer_state *pfb = &ctx->framebuffer;
- struct fd_batch *batch = ctx->batch;
- struct fd_ringbuffer *ring = ctx->ring;
+ struct pipe_framebuffer_state *pfb = &batch->framebuffer;
+ struct fd_ringbuffer *ring = batch->gmem;
int i;
uint32_t x1 = gmem->minx;
@@ -804,7 +807,7 @@ emit_binning_pass(struct fd_context *ctx)
uint32_t y2 = gmem->miny + gmem->height - 1;
if (ctx->screen->gpu_id == 320) {
- emit_binning_workaround(ctx);
+ emit_binning_workaround(batch);
fd_wfi(ctx, ring);
OUT_PKT3(ring, CP_INVALIDATE_STATE, 1);
OUT_RING(ring, 0x00007fff);
@@ -912,19 +915,19 @@ emit_binning_pass(struct fd_context *ctx)
fd_wfi(ctx, ring);
if (ctx->screen->gpu_id == 320) {
- emit_binning_workaround(ctx);
+ emit_binning_workaround(batch);
}
}
/* before first tile */
static void
-fd3_emit_tile_init(struct fd_context *ctx)
+fd3_emit_tile_init(struct fd_batch *batch)
{
- struct fd_ringbuffer *ring = ctx->ring;
- struct fd_gmem_stateobj *gmem = &ctx->gmem;
+ struct fd_ringbuffer *ring = batch->gmem;
+ struct fd_gmem_stateobj *gmem = &batch->ctx->gmem;
uint32_t rb_render_control;
- fd3_emit_restore(ctx, ring);
+ fd3_emit_restore(batch->ctx, ring);
/* note: use gmem->bin_w/h, the bin_w/h parameters may be truncated
* at the right and bottom edge tiles
@@ -933,29 +936,30 @@ fd3_emit_tile_init(struct fd_context *ctx)
OUT_RING(ring, A3XX_VSC_BIN_SIZE_WIDTH(gmem->bin_w) |
A3XX_VSC_BIN_SIZE_HEIGHT(gmem->bin_h));
- update_vsc_pipe(ctx);
+ update_vsc_pipe(batch);
- if (use_hw_binning(ctx)) {
+ if (use_hw_binning(batch)) {
/* emit hw binning pass: */
- emit_binning_pass(ctx);
+ emit_binning_pass(batch);
- patch_draws(ctx, USE_VISIBILITY);
+ patch_draws(batch, USE_VISIBILITY);
} else {
- patch_draws(ctx, IGNORE_VISIBILITY);
+ patch_draws(batch, IGNORE_VISIBILITY);
}
rb_render_control = A3XX_RB_RENDER_CONTROL_ENABLE_GMEM |
A3XX_RB_RENDER_CONTROL_BIN_WIDTH(gmem->bin_w);
- patch_rbrc(ctx, rb_render_control);
+ patch_rbrc(batch, rb_render_control);
}
/* before mem2gmem */
static void
-fd3_emit_tile_prep(struct fd_context *ctx, struct fd_tile *tile)
+fd3_emit_tile_prep(struct fd_batch *batch, struct fd_tile *tile)
{
- struct fd_ringbuffer *ring = ctx->ring;
- struct pipe_framebuffer_state *pfb = &ctx->framebuffer;
+ struct fd_context *ctx = batch->ctx;
+ struct fd_ringbuffer *ring = batch->gmem;
+ struct pipe_framebuffer_state *pfb = &batch->framebuffer;
if (ctx->needs_rb_fbd) {
fd_wfi(ctx, ring);
@@ -973,12 +977,13 @@ fd3_emit_tile_prep(struct fd_context *ctx, struct fd_tile *tile)
/* before IB to rendering cmds: */
static void
-fd3_emit_tile_renderprep(struct fd_context *ctx, struct fd_tile *tile)
+fd3_emit_tile_renderprep(struct fd_batch *batch, struct fd_tile *tile)
{
+ struct fd_context *ctx = batch->ctx;
struct fd3_context *fd3_ctx = fd3_context(ctx);
- struct fd_ringbuffer *ring = ctx->ring;
+ struct fd_ringbuffer *ring = batch->gmem;
struct fd_gmem_stateobj *gmem = &ctx->gmem;
- struct pipe_framebuffer_state *pfb = &ctx->framebuffer;
+ struct pipe_framebuffer_state *pfb = &batch->framebuffer;
uint32_t x1 = tile->xoff;
uint32_t y1 = tile->yoff;
@@ -1005,7 +1010,7 @@ fd3_emit_tile_renderprep(struct fd_context *ctx, struct fd_tile *tile)
OUT_RING(ring, 0x00000000);
}
- if (use_hw_binning(ctx)) {
+ if (use_hw_binning(batch)) {
struct fd_vsc_pipe *pipe = &ctx->pipe[tile->p];
assert(pipe->w * pipe->h);
generated by cgit v1.2.3 (git 2.39.1) at 2024-12-12 14:51:35 +0000