diff options
Diffstat (limited to 'src/amd')
| -rw-r--r-- | src/amd/common/ac_surface.c | 13 | ||||
| -rw-r--r-- | src/amd/common/ac_surface.h | 1 |
2 files changed, 11 insertions, 3 deletions
diff --git a/src/amd/common/ac_surface.c b/src/amd/common/ac_surface.c index 2c2917d4a23..1d254ec3a78 100644 --- a/src/amd/common/ac_surface.c +++ b/src/amd/common/ac_surface.c @@ -338,11 +338,12 @@ static int gfx6_compute_level(ADDR_HANDLE addrlib, } } - /* TC-compatible HTILE. */ + /* HTILE. */ if (!is_stencil && AddrSurfInfoIn->flags.depth && surf_level->mode == RADEON_SURF_MODE_2D && - level == 0) { + level == 0 && + !(surf->flags & RADEON_SURF_NO_HTILE)) { AddrHtileIn->flags.tcCompatible = AddrSurfInfoIn->flags.tcCompatible; AddrHtileIn->pitch = AddrSurfInfoOut->pitch; AddrHtileIn->height = AddrSurfInfoOut->height; @@ -1065,6 +1066,9 @@ static int gfx9_compute_miptree(ADDR_HANDLE addrlib, if (in->flags.depth) { assert(in->swizzleMode != ADDR_SW_LINEAR); + if (surf->flags & RADEON_SURF_NO_HTILE) + return 0; + /* HTILE */ ADDR2_COMPUTE_HTILE_INFO_INPUT hin = {0}; ADDR2_COMPUTE_HTILE_INFO_OUTPUT hout = {0}; @@ -1091,7 +1095,10 @@ static int gfx9_compute_miptree(ADDR_HANDLE addrlib, surf->htile_size = hout.htileBytes; surf->htile_slice_size = hout.sliceSize; surf->htile_alignment = hout.baseAlign; - } else { + return 0; + } + + { /* Compute tile swizzle for the color surface. * All *_X and *_T modes can use the swizzle. */ diff --git a/src/amd/common/ac_surface.h b/src/amd/common/ac_surface.h index 53074c90faf..52aa63bff2e 100644 --- a/src/amd/common/ac_surface.h +++ b/src/amd/common/ac_surface.h @@ -72,6 +72,7 @@ enum radeon_micro_mode { #define RADEON_SURF_NO_RENDER_TARGET (1 << 27) #define RADEON_SURF_FORCE_SWIZZLE_MODE (1 << 28) #define RADEON_SURF_NO_FMASK (1 << 29) +#define RADEON_SURF_NO_HTILE (1 << 30) struct legacy_surf_level { uint64_t offset; |