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Diffstat (limited to 'src/amd/vulkan/radv_image.c')
-rw-r--r--src/amd/vulkan/radv_image.c11
1 files changed, 10 insertions, 1 deletions
diff --git a/src/amd/vulkan/radv_image.c b/src/amd/vulkan/radv_image.c
index 17ee74b5f5b..a8af4fd6d68 100644
--- a/src/amd/vulkan/radv_image.c
+++ b/src/amd/vulkan/radv_image.c
@@ -32,6 +32,7 @@
#include "sid.h"
#include "gfx9d.h"
#include "util/debug.h"
+#include "util/u_atomic.h"
static unsigned
radv_choose_tiling(struct radv_device *Device,
const struct radv_image_create_info *create_info)
@@ -210,6 +211,8 @@ si_set_mutable_tex_desc_fields(struct radv_device *device,
va += base_level_info->offset;
state[0] = va >> 8;
+ if (chip_class < GFX9)
+ state[0] |= image->surface.u.legacy.tile_swizzle;
state[1] &= C_008F14_BASE_ADDRESS_HI;
state[1] |= S_008F14_BASE_ADDRESS_HI(va >> 40);
state[3] |= S_008F1C_TILING_INDEX(si_tile_mode_index(image, base_level,
@@ -225,7 +228,8 @@ si_set_mutable_tex_desc_fields(struct radv_device *device,
meta_va += base_level_info->dcc_offset;
state[6] |= S_008F28_COMPRESSION_EN(1);
state[7] = meta_va >> 8;
-
+ if (chip_class < GFX9)
+ state[7] |= image->surface.u.legacy.tile_swizzle;
}
}
@@ -473,6 +477,8 @@ si_make_texture_descriptor(struct radv_device *device,
}
fmask_state[0] = va >> 8;
+ if (device->physical_device->rad_info.chip_class < GFX9)
+ fmask_state[0] |= image->surface.u.legacy.tile_swizzle;
fmask_state[1] = S_008F14_BASE_ADDRESS_HI(va >> 40) |
S_008F14_DATA_FORMAT_GFX6(fmask_format) |
S_008F14_NUM_FORMAT_GFX6(num_format);
@@ -792,6 +798,9 @@ radv_image_create(VkDevice _device,
image->shareable = vk_find_struct_const(pCreateInfo->pNext,
EXTERNAL_MEMORY_IMAGE_CREATE_INFO_KHR) != NULL;
+ if (!vk_format_is_depth(pCreateInfo->format) && !create_info->scanout && !image->shareable) {
+ image->info.surf_index = p_atomic_inc_return(&device->image_mrt_offset_counter) - 1;
+ }
radv_init_surface(device, &image->surface, create_info);