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-rw-r--r--src/intel/compiler/brw_compiler.h1
-rw-r--r--src/intel/compiler/brw_fs_nir.cpp47
-rw-r--r--src/intel/compiler/brw_shader.cpp32
-rw-r--r--src/intel/compiler/brw_shader.h2
-rw-r--r--src/intel/compiler/brw_vec4_nir.cpp46
-rw-r--r--src/mesa/drivers/dri/i965/brw_link.cpp2
-rw-r--r--src/mesa/drivers/dri/i965/brw_program.c12
-rw-r--r--src/mesa/drivers/dri/i965/brw_wm_surface_state.c5
8 files changed, 8 insertions, 139 deletions
diff --git a/src/intel/compiler/brw_compiler.h b/src/intel/compiler/brw_compiler.h
index df6ee018546..c17eaed946e 100644
--- a/src/intel/compiler/brw_compiler.h
+++ b/src/intel/compiler/brw_compiler.h
@@ -581,7 +581,6 @@ struct brw_stage_prog_data {
uint32_t gather_texture_start;
uint32_t ubo_start;
uint32_t ssbo_start;
- uint32_t abo_start;
uint32_t image_start;
uint32_t shader_time_start;
uint32_t plane_start[3];
diff --git a/src/intel/compiler/brw_fs_nir.cpp b/src/intel/compiler/brw_fs_nir.cpp
index ca3707db90f..bed1cd3b492 100644
--- a/src/intel/compiler/brw_fs_nir.cpp
+++ b/src/intel/compiler/brw_fs_nir.cpp
@@ -3645,53 +3645,6 @@ fs_visitor::nir_emit_intrinsic(const fs_builder &bld, nir_intrinsic_instr *instr
dest = get_nir_dest(instr->dest);
switch (instr->intrinsic) {
- case nir_intrinsic_atomic_counter_inc:
- case nir_intrinsic_atomic_counter_dec:
- case nir_intrinsic_atomic_counter_read:
- case nir_intrinsic_atomic_counter_add:
- case nir_intrinsic_atomic_counter_min:
- case nir_intrinsic_atomic_counter_max:
- case nir_intrinsic_atomic_counter_and:
- case nir_intrinsic_atomic_counter_or:
- case nir_intrinsic_atomic_counter_xor:
- case nir_intrinsic_atomic_counter_exchange:
- case nir_intrinsic_atomic_counter_comp_swap: {
- if (stage == MESA_SHADER_FRAGMENT &&
- instr->intrinsic != nir_intrinsic_atomic_counter_read)
- brw_wm_prog_data(prog_data)->has_side_effects = true;
-
- /* Get some metadata from the image intrinsic. */
- const nir_intrinsic_info *info = &nir_intrinsic_infos[instr->intrinsic];
-
- /* Get the arguments of the atomic intrinsic. */
- const fs_reg offset = get_nir_src(instr->src[0]);
- const unsigned surface = (stage_prog_data->binding_table.abo_start +
- instr->const_index[0]);
- const fs_reg src0 = (info->num_srcs >= 2
- ? get_nir_src(instr->src[1]) : fs_reg());
- const fs_reg src1 = (info->num_srcs >= 3
- ? get_nir_src(instr->src[2]) : fs_reg());
- fs_reg tmp;
-
- assert(info->num_srcs <= 3);
-
- /* Emit a surface read or atomic op. */
- if (instr->intrinsic == nir_intrinsic_atomic_counter_read) {
- tmp = emit_untyped_read(bld, brw_imm_ud(surface), offset, 1, 1);
- } else {
- tmp = emit_untyped_atomic(bld, brw_imm_ud(surface), offset, src0,
- src1, 1, 1,
- get_atomic_counter_op(instr->intrinsic));
- }
-
- /* Assign the result. */
- bld.MOV(retype(dest, BRW_REGISTER_TYPE_UD), tmp);
-
- /* Mark the surface as used. */
- brw_mark_surface_used(stage_prog_data, surface);
- break;
- }
-
case nir_intrinsic_image_load:
case nir_intrinsic_image_store:
case nir_intrinsic_image_atomic_add:
diff --git a/src/intel/compiler/brw_shader.cpp b/src/intel/compiler/brw_shader.cpp
index b27a71c3c27..ba61481a0af 100644
--- a/src/intel/compiler/brw_shader.cpp
+++ b/src/intel/compiler/brw_shader.cpp
@@ -622,38 +622,6 @@ brw_abs_immediate(enum brw_reg_type type, struct brw_reg *reg)
return false;
}
-/**
- * Get the appropriate atomic op for an image atomic intrinsic.
- */
-unsigned
-get_atomic_counter_op(nir_intrinsic_op op)
-{
- switch (op) {
- case nir_intrinsic_atomic_counter_inc:
- return BRW_AOP_INC;
- case nir_intrinsic_atomic_counter_dec:
- return BRW_AOP_PREDEC;
- case nir_intrinsic_atomic_counter_add:
- return BRW_AOP_ADD;
- case nir_intrinsic_atomic_counter_min:
- return BRW_AOP_UMIN;
- case nir_intrinsic_atomic_counter_max:
- return BRW_AOP_UMAX;
- case nir_intrinsic_atomic_counter_and:
- return BRW_AOP_AND;
- case nir_intrinsic_atomic_counter_or:
- return BRW_AOP_OR;
- case nir_intrinsic_atomic_counter_xor:
- return BRW_AOP_XOR;
- case nir_intrinsic_atomic_counter_exchange:
- return BRW_AOP_MOV;
- case nir_intrinsic_atomic_counter_comp_swap:
- return BRW_AOP_CMPWR;
- default:
- unreachable("Not reachable.");
- }
-}
-
backend_shader::backend_shader(const struct brw_compiler *compiler,
void *log_data,
void *mem_ctx,
diff --git a/src/intel/compiler/brw_shader.h b/src/intel/compiler/brw_shader.h
index ed434acf5a0..06abdc4d175 100644
--- a/src/intel/compiler/brw_shader.h
+++ b/src/intel/compiler/brw_shader.h
@@ -286,8 +286,6 @@ struct brw_gs_compile
unsigned control_data_header_size_bits;
};
-unsigned get_atomic_counter_op(nir_intrinsic_op op);
-
#ifdef __cplusplus
}
#endif
diff --git a/src/intel/compiler/brw_vec4_nir.cpp b/src/intel/compiler/brw_vec4_nir.cpp
index 0a1caa9fad8..c4ea24b8db7 100644
--- a/src/intel/compiler/brw_vec4_nir.cpp
+++ b/src/intel/compiler/brw_vec4_nir.cpp
@@ -804,52 +804,6 @@ vec4_visitor::nir_emit_intrinsic(nir_intrinsic_instr *instr)
break;
}
- case nir_intrinsic_atomic_counter_inc:
- case nir_intrinsic_atomic_counter_dec:
- case nir_intrinsic_atomic_counter_read:
- case nir_intrinsic_atomic_counter_add:
- case nir_intrinsic_atomic_counter_min:
- case nir_intrinsic_atomic_counter_max:
- case nir_intrinsic_atomic_counter_and:
- case nir_intrinsic_atomic_counter_or:
- case nir_intrinsic_atomic_counter_xor:
- case nir_intrinsic_atomic_counter_exchange:
- case nir_intrinsic_atomic_counter_comp_swap: {
- unsigned surf_index = prog_data->base.binding_table.abo_start +
- (unsigned) instr->const_index[0];
- const vec4_builder bld =
- vec4_builder(this).at_end().annotate(current_annotation, base_ir);
-
- /* Get some metadata from the image intrinsic. */
- const nir_intrinsic_info *info = &nir_intrinsic_infos[instr->intrinsic];
-
- /* Get the arguments of the atomic intrinsic. */
- src_reg offset = get_nir_src(instr->src[0], nir_type_int32,
- instr->num_components);
- const src_reg surface = brw_imm_ud(surf_index);
- const src_reg src0 = (info->num_srcs >= 2
- ? get_nir_src(instr->src[1]) : src_reg());
- const src_reg src1 = (info->num_srcs >= 3
- ? get_nir_src(instr->src[2]) : src_reg());
-
- src_reg tmp;
-
- dest = get_nir_dest(instr->dest);
-
- if (instr->intrinsic == nir_intrinsic_atomic_counter_read) {
- tmp = emit_untyped_read(bld, surface, offset, 1, 1);
- } else {
- tmp = emit_untyped_atomic(bld, surface, offset,
- src0, src1,
- 1, 1,
- get_atomic_counter_op(instr->intrinsic));
- }
-
- bld.MOV(retype(dest, tmp.type), tmp);
- brw_mark_surface_used(stage_prog_data, surf_index);
- break;
- }
-
case nir_intrinsic_load_ubo: {
nir_const_value *const_block_index = nir_src_as_const_value(instr->src[0]);
src_reg surf_index;
diff --git a/src/mesa/drivers/dri/i965/brw_link.cpp b/src/mesa/drivers/dri/i965/brw_link.cpp
index 24545d52ecb..d18521e792d 100644
--- a/src/mesa/drivers/dri/i965/brw_link.cpp
+++ b/src/mesa/drivers/dri/i965/brw_link.cpp
@@ -299,6 +299,8 @@ brw_link_shader(struct gl_context *ctx, struct gl_shader_program *shProg)
NIR_PASS_V(prog->nir, nir_lower_samplers, shProg);
NIR_PASS_V(prog->nir, nir_lower_atomics, shProg);
+ NIR_PASS_V(prog->nir, nir_lower_atomics_to_ssbo,
+ prog->nir->info.num_abos);
if (brw->ctx.Cache) {
struct blob writer;
diff --git a/src/mesa/drivers/dri/i965/brw_program.c b/src/mesa/drivers/dri/i965/brw_program.c
index 5ecfb9f5b11..755d4973cc0 100644
--- a/src/mesa/drivers/dri/i965/brw_program.c
+++ b/src/mesa/drivers/dri/i965/brw_program.c
@@ -732,10 +732,11 @@ brw_assign_common_binding_table_offsets(const struct gen_device_info *devinfo,
stage_prog_data->binding_table.ubo_start = 0xd0d0d0d0;
}
- if (prog->info.num_ssbos) {
+ if (prog->info.num_ssbos || prog->info.num_abos) {
+ assert(prog->info.num_abos <= BRW_MAX_ABO);
assert(prog->info.num_ssbos <= BRW_MAX_SSBO);
stage_prog_data->binding_table.ssbo_start = next_binding_table_offset;
- next_binding_table_offset += prog->info.num_ssbos;
+ next_binding_table_offset += prog->info.num_abos + prog->info.num_ssbos;
} else {
stage_prog_data->binding_table.ssbo_start = 0xd0d0d0d0;
}
@@ -759,13 +760,6 @@ brw_assign_common_binding_table_offsets(const struct gen_device_info *devinfo,
stage_prog_data->binding_table.gather_texture_start = 0xd0d0d0d0;
}
- if (prog->info.num_abos) {
- stage_prog_data->binding_table.abo_start = next_binding_table_offset;
- next_binding_table_offset += prog->info.num_abos;
- } else {
- stage_prog_data->binding_table.abo_start = 0xd0d0d0d0;
- }
-
if (prog->info.num_images) {
stage_prog_data->binding_table.image_start = next_binding_table_offset;
next_binding_table_offset += prog->info.num_images;
diff --git a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
index bcd82d03e7c..a4804401fc5 100644
--- a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
+++ b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
@@ -1284,7 +1284,8 @@ brw_upload_ubo_surfaces(struct brw_context *brw, struct gl_program *prog,
}
uint32_t *ssbo_surf_offsets =
- &stage_state->surf_offset[prog_data->binding_table.ssbo_start];
+ &stage_state->surf_offset[prog_data->binding_table.ssbo_start] +
+ prog->info.num_abos;
for (int i = 0; i < prog->info.num_ssbos; i++) {
struct gl_buffer_binding *binding =
@@ -1351,7 +1352,7 @@ brw_upload_abo_surfaces(struct brw_context *brw,
{
struct gl_context *ctx = &brw->ctx;
uint32_t *surf_offsets =
- &stage_state->surf_offset[prog_data->binding_table.abo_start];
+ &stage_state->surf_offset[prog_data->binding_table.ssbo_start];
if (prog->info.num_abos) {
for (unsigned i = 0; i < prog->info.num_abos; i++) {
generated by cgit v1.2.3 (git 2.39.1) at 2024-12-03 06:08:21 +0000