diff options
| -rw-r--r-- | src/amd/common/gfx9d.h | 60 | ||||
| -rw-r--r-- | src/amd/common/sid.h | 60 | ||||
| -rw-r--r-- | src/amd/vulkan/radv_image.c | 6 | ||||
| -rw-r--r-- | src/gallium/drivers/radeonsi/si_descriptors.c | 4 | ||||
| -rw-r--r-- | src/gallium/drivers/radeonsi/si_state.c | 2 |
5 files changed, 66 insertions, 66 deletions
diff --git a/src/amd/common/gfx9d.h b/src/amd/common/gfx9d.h index fa4e4cd15b3..702508bfb39 100644 --- a/src/amd/common/gfx9d.h +++ b/src/amd/common/gfx9d.h @@ -1339,9 +1339,9 @@ #define S_008F20_DEPTH(x) (((unsigned)(x) & 0x1FFF) << 0) #define G_008F20_DEPTH(x) (((x) >> 0) & 0x1FFF) #define C_008F20_DEPTH 0xFFFFE000 -#define S_008F20_PITCH(x) (((unsigned)(x) & 0xFFFF) << 13) -#define G_008F20_PITCH(x) (((x) >> 13) & 0xFFFF) -#define C_008F20_PITCH 0xE0001FFF +#define S_008F20_PITCH_GFX9(x) (((unsigned)(x) & 0xFFFF) << 13) +#define G_008F20_PITCH_GFX9(x) (((x) >> 13) & 0xFFFF) +#define C_008F20_PITCH_GFX9 0xE0001FFF #define S_008F20_BC_SWIZZLE(x) (((unsigned)(x) & 0x07) << 29) #define G_008F20_BC_SWIZZLE(x) (((x) >> 29) & 0x07) #define C_008F20_BC_SWIZZLE 0x1FFFFFFF @@ -1568,9 +1568,9 @@ #define S_0098F8_NUM_PIPES(x) (((unsigned)(x) & 0x07) << 0) #define G_0098F8_NUM_PIPES(x) (((x) >> 0) & 0x07) #define C_0098F8_NUM_PIPES 0xFFFFFFF8 -#define S_0098F8_PIPE_INTERLEAVE_SIZE(x) (((unsigned)(x) & 0x07) << 3) -#define G_0098F8_PIPE_INTERLEAVE_SIZE(x) (((x) >> 3) & 0x07) -#define C_0098F8_PIPE_INTERLEAVE_SIZE 0xFFFFFFC7 +#define S_0098F8_PIPE_INTERLEAVE_SIZE_GFX9(x) (((unsigned)(x) & 0x07) << 3) +#define G_0098F8_PIPE_INTERLEAVE_SIZE_GFX9(x) (((x) >> 3) & 0x07) +#define C_0098F8_PIPE_INTERLEAVE_SIZE_GFX9 0xFFFFFFC7 #define S_0098F8_MAX_COMPRESSED_FRAGS(x) (((unsigned)(x) & 0x03) << 6) #define G_0098F8_MAX_COMPRESSED_FRAGS(x) (((x) >> 6) & 0x03) #define C_0098F8_MAX_COMPRESSED_FRAGS 0xFFFFFF3F @@ -1583,12 +1583,12 @@ #define S_0098F8_SHADER_ENGINE_TILE_SIZE(x) (((unsigned)(x) & 0x07) << 16) #define G_0098F8_SHADER_ENGINE_TILE_SIZE(x) (((x) >> 16) & 0x07) #define C_0098F8_SHADER_ENGINE_TILE_SIZE 0xFFF8FFFF -#define S_0098F8_NUM_SHADER_ENGINES(x) (((unsigned)(x) & 0x03) << 19) -#define G_0098F8_NUM_SHADER_ENGINES(x) (((x) >> 19) & 0x03) -#define C_0098F8_NUM_SHADER_ENGINES 0xFFE7FFFF -#define S_0098F8_NUM_GPUS(x) (((unsigned)(x) & 0x07) << 21) -#define G_0098F8_NUM_GPUS(x) (((x) >> 21) & 0x07) -#define C_0098F8_NUM_GPUS 0xFF1FFFFF +#define S_0098F8_NUM_SHADER_ENGINES_GFX9(x) (((unsigned)(x) & 0x03) << 19) +#define G_0098F8_NUM_SHADER_ENGINES_GFX9(x) (((x) >> 19) & 0x03) +#define C_0098F8_NUM_SHADER_ENGINES_GFX9 0xFFE7FFFF +#define S_0098F8_NUM_GPUS_GFX9(x) (((unsigned)(x) & 0x07) << 21) +#define G_0098F8_NUM_GPUS_GFX9(x) (((x) >> 21) & 0x07) +#define C_0098F8_NUM_GPUS_GFX9 0xFF1FFFFF #define S_0098F8_MULTI_GPU_TILE_SIZE(x) (((unsigned)(x) & 0x03) << 24) #define G_0098F8_MULTI_GPU_TILE_SIZE(x) (((x) >> 24) & 0x03) #define C_0098F8_MULTI_GPU_TILE_SIZE 0xFCFFFFFF @@ -4253,22 +4253,22 @@ #define S_028350_SE_MAP(x) (((unsigned)(x) & 0x03) << 24) #define G_028350_SE_MAP(x) (((x) >> 24) & 0x03) #define C_028350_SE_MAP 0xFCFFFFFF -#define S_028350_SE_XSEL(x) (((unsigned)(x) & 0x07) << 26) -#define G_028350_SE_XSEL(x) (((x) >> 26) & 0x07) -#define C_028350_SE_XSEL 0xE3FFFFFF -#define S_028350_SE_YSEL(x) (((unsigned)(x) & 0x07) << 29) -#define G_028350_SE_YSEL(x) (((x) >> 29) & 0x07) -#define C_028350_SE_YSEL 0x1FFFFFFF +#define S_028350_SE_XSEL_GFX9(x) (((unsigned)(x) & 0x07) << 26) +#define G_028350_SE_XSEL_GFX9(x) (((x) >> 26) & 0x07) +#define C_028350_SE_XSEL_GFX9 0xE3FFFFFF +#define S_028350_SE_YSEL_GFX9(x) (((unsigned)(x) & 0x07) << 29) +#define G_028350_SE_YSEL_GFX9(x) (((x) >> 29) & 0x07) +#define C_028350_SE_YSEL_GFX9 0x1FFFFFFF #define R_028354_PA_SC_RASTER_CONFIG_1 0x028354 #define S_028354_SE_PAIR_MAP(x) (((unsigned)(x) & 0x03) << 0) #define G_028354_SE_PAIR_MAP(x) (((x) >> 0) & 0x03) #define C_028354_SE_PAIR_MAP 0xFFFFFFFC -#define S_028354_SE_PAIR_XSEL(x) (((unsigned)(x) & 0x07) << 2) -#define G_028354_SE_PAIR_XSEL(x) (((x) >> 2) & 0x07) -#define C_028354_SE_PAIR_XSEL 0xFFFFFFE3 -#define S_028354_SE_PAIR_YSEL(x) (((unsigned)(x) & 0x07) << 5) -#define G_028354_SE_PAIR_YSEL(x) (((x) >> 5) & 0x07) -#define C_028354_SE_PAIR_YSEL 0xFFFFFF1F +#define S_028354_SE_PAIR_XSEL_GFX9(x) (((unsigned)(x) & 0x07) << 2) +#define G_028354_SE_PAIR_XSEL_GFX9(x) (((x) >> 2) & 0x07) +#define C_028354_SE_PAIR_XSEL_GFX9 0xFFFFFFE3 +#define S_028354_SE_PAIR_YSEL_GFX9(x) (((unsigned)(x) & 0x07) << 5) +#define G_028354_SE_PAIR_YSEL_GFX9(x) (((x) >> 5) & 0x07) +#define C_028354_SE_PAIR_YSEL_GFX9 0xFFFFFF1F #define R_028358_PA_SC_SCREEN_EXTENT_CONTROL 0x028358 #define S_028358_SLICE_EVEN_ENABLE(x) (((unsigned)(x) & 0x03) << 0) #define G_028358_SLICE_EVEN_ENABLE(x) (((x) >> 0) & 0x03) @@ -5144,9 +5144,9 @@ #define R_0287DC_PA_CL_POINT_SIZE 0x0287DC #define R_0287E0_PA_CL_POINT_CULL_RAD 0x0287E0 #define R_0287E4_VGT_DMA_BASE_HI 0x0287E4 -#define S_0287E4_BASE_ADDR(x) (((unsigned)(x) & 0xFFFF) << 0) -#define G_0287E4_BASE_ADDR(x) (((x) >> 0) & 0xFFFF) -#define C_0287E4_BASE_ADDR 0xFFFF0000 +#define S_0287E4_BASE_ADDR_GFX9(x) (((unsigned)(x) & 0xFFFF) << 0) +#define G_0287E4_BASE_ADDR_GFX9(x) (((x) >> 0) & 0xFFFF) +#define C_0287E4_BASE_ADDR_GFX9 0xFFFF0000 #define R_0287E8_VGT_DMA_BASE 0x0287E8 #define R_0287F0_VGT_DRAW_INITIATOR 0x0287F0 #define S_0287F0_SOURCE_SELECT(x) (((unsigned)(x) & 0x03) << 0) @@ -6065,9 +6065,9 @@ #define S_028A90_EVENT_TYPE(x) (((unsigned)(x) & 0x3F) << 0) #define G_028A90_EVENT_TYPE(x) (((x) >> 0) & 0x3F) #define C_028A90_EVENT_TYPE 0xFFFFFFC0 -#define S_028A90_ADDRESS_HI(x) (((unsigned)(x) & 0x1FFFF) << 10) -#define G_028A90_ADDRESS_HI(x) (((x) >> 10) & 0x1FFFF) -#define C_028A90_ADDRESS_HI 0xF80003FF +#define S_028A90_ADDRESS_HI_GFX9(x) (((unsigned)(x) & 0x1FFFF) << 10) +#define G_028A90_ADDRESS_HI_GFX9(x) (((x) >> 10) & 0x1FFFF) +#define C_028A90_ADDRESS_HI_GFX9 0xF80003FF #define S_028A90_EXTENDED_EVENT(x) (((unsigned)(x) & 0x1) << 27) #define G_028A90_EXTENDED_EVENT(x) (((x) >> 27) & 0x1) #define C_028A90_EXTENDED_EVENT 0xF7FFFFFF diff --git a/src/amd/common/sid.h b/src/amd/common/sid.h index cb353d6f81e..9145624db33 100644 --- a/src/amd/common/sid.h +++ b/src/amd/common/sid.h @@ -2261,9 +2261,9 @@ #define S_008F20_DEPTH(x) (((unsigned)(x) & 0x1FFF) << 0) #define G_008F20_DEPTH(x) (((x) >> 0) & 0x1FFF) #define C_008F20_DEPTH 0xFFFFE000 -#define S_008F20_PITCH(x) (((unsigned)(x) & 0x3FFF) << 13) -#define G_008F20_PITCH(x) (((x) >> 13) & 0x3FFF) -#define C_008F20_PITCH 0xF8001FFF +#define S_008F20_PITCH_GFX6(x) (((unsigned)(x) & 0x3FFF) << 13) +#define G_008F20_PITCH_GFX6(x) (((x) >> 13) & 0x3FFF) +#define C_008F20_PITCH_GFX6 0xF8001FFF #define R_008F24_SQ_IMG_RSRC_WORD5 0x008F24 #define S_008F24_BASE_ARRAY(x) (((unsigned)(x) & 0x1FFF) << 0) #define G_008F24_BASE_ARRAY(x) (((x) >> 0) & 0x1FFF) @@ -2674,21 +2674,21 @@ #define S_0098F8_NUM_PIPES(x) (((unsigned)(x) & 0x07) << 0) #define G_0098F8_NUM_PIPES(x) (((x) >> 0) & 0x07) #define C_0098F8_NUM_PIPES 0xFFFFFFF8 -#define S_0098F8_PIPE_INTERLEAVE_SIZE(x) (((unsigned)(x) & 0x07) << 4) -#define G_0098F8_PIPE_INTERLEAVE_SIZE(x) (((x) >> 4) & 0x07) -#define C_0098F8_PIPE_INTERLEAVE_SIZE 0xFFFFFF8F +#define S_0098F8_PIPE_INTERLEAVE_SIZE_GFX6(x) (((unsigned)(x) & 0x07) << 4) +#define G_0098F8_PIPE_INTERLEAVE_SIZE_GFX6(x) (((x) >> 4) & 0x07) +#define C_0098F8_PIPE_INTERLEAVE_SIZE_GFX6 0xFFFFFF8F #define S_0098F8_BANK_INTERLEAVE_SIZE(x) (((unsigned)(x) & 0x07) << 8) #define G_0098F8_BANK_INTERLEAVE_SIZE(x) (((x) >> 8) & 0x07) #define C_0098F8_BANK_INTERLEAVE_SIZE 0xFFFFF8FF -#define S_0098F8_NUM_SHADER_ENGINES(x) (((unsigned)(x) & 0x03) << 12) -#define G_0098F8_NUM_SHADER_ENGINES(x) (((x) >> 12) & 0x03) -#define C_0098F8_NUM_SHADER_ENGINES 0xFFFFCFFF +#define S_0098F8_NUM_SHADER_ENGINES_GFX6(x) (((unsigned)(x) & 0x03) << 12) +#define G_0098F8_NUM_SHADER_ENGINES_GFX6(x) (((x) >> 12) & 0x03) +#define C_0098F8_NUM_SHADER_ENGINES_GFX6 0xFFFFCFFF #define S_0098F8_SHADER_ENGINE_TILE_SIZE(x) (((unsigned)(x) & 0x07) << 16) #define G_0098F8_SHADER_ENGINE_TILE_SIZE(x) (((x) >> 16) & 0x07) #define C_0098F8_SHADER_ENGINE_TILE_SIZE 0xFFF8FFFF -#define S_0098F8_NUM_GPUS(x) (((unsigned)(x) & 0x07) << 20) -#define G_0098F8_NUM_GPUS(x) (((x) >> 20) & 0x07) -#define C_0098F8_NUM_GPUS 0xFF8FFFFF +#define S_0098F8_NUM_GPUS_GFX6(x) (((unsigned)(x) & 0x07) << 20) +#define G_0098F8_NUM_GPUS_GFX6(x) (((x) >> 20) & 0x07) +#define C_0098F8_NUM_GPUS_GFX6 0xFF8FFFFF #define S_0098F8_MULTI_GPU_TILE_SIZE(x) (((unsigned)(x) & 0x03) << 24) #define G_0098F8_MULTI_GPU_TILE_SIZE(x) (((x) >> 24) & 0x03) #define C_0098F8_MULTI_GPU_TILE_SIZE 0xFCFFFFFF @@ -5514,16 +5514,16 @@ #define V_028350_RASTER_CONFIG_SE_MAP_1 0x01 #define V_028350_RASTER_CONFIG_SE_MAP_2 0x02 #define V_028350_RASTER_CONFIG_SE_MAP_3 0x03 -#define S_028350_SE_XSEL(x) (((unsigned)(x) & 0x03) << 26) -#define G_028350_SE_XSEL(x) (((x) >> 26) & 0x03) -#define C_028350_SE_XSEL 0xF3FFFFFF +#define S_028350_SE_XSEL_GFX6(x) (((unsigned)(x) & 0x03) << 26) +#define G_028350_SE_XSEL_GFX6(x) (((x) >> 26) & 0x03) +#define C_028350_SE_XSEL_GFX6 0xF3FFFFFF #define V_028350_RASTER_CONFIG_SE_XSEL_8_WIDE_TILE 0x00 #define V_028350_RASTER_CONFIG_SE_XSEL_16_WIDE_TILE 0x01 #define V_028350_RASTER_CONFIG_SE_XSEL_32_WIDE_TILE 0x02 #define V_028350_RASTER_CONFIG_SE_XSEL_64_WIDE_TILE 0x03 -#define S_028350_SE_YSEL(x) (((unsigned)(x) & 0x03) << 28) -#define G_028350_SE_YSEL(x) (((x) >> 28) & 0x03) -#define C_028350_SE_YSEL 0xCFFFFFFF +#define S_028350_SE_YSEL_GFX6(x) (((unsigned)(x) & 0x03) << 28) +#define G_028350_SE_YSEL_GFX6(x) (((x) >> 28) & 0x03) +#define C_028350_SE_YSEL_GFX6 0xCFFFFFFF #define V_028350_RASTER_CONFIG_SE_YSEL_8_WIDE_TILE 0x00 #define V_028350_RASTER_CONFIG_SE_YSEL_16_WIDE_TILE 0x01 #define V_028350_RASTER_CONFIG_SE_YSEL_32_WIDE_TILE 0x02 @@ -5537,16 +5537,16 @@ #define V_028354_RASTER_CONFIG_SE_PAIR_MAP_1 0x01 #define V_028354_RASTER_CONFIG_SE_PAIR_MAP_2 0x02 #define V_028354_RASTER_CONFIG_SE_PAIR_MAP_3 0x03 -#define S_028354_SE_PAIR_XSEL(x) (((unsigned)(x) & 0x03) << 2) -#define G_028354_SE_PAIR_XSEL(x) (((x) >> 2) & 0x03) -#define C_028354_SE_PAIR_XSEL 0xFFFFFFF3 +#define S_028354_SE_PAIR_XSEL_GFX6(x) (((unsigned)(x) & 0x03) << 2) +#define G_028354_SE_PAIR_XSEL_GFX6(x) (((x) >> 2) & 0x03) +#define C_028354_SE_PAIR_XSEL_GFX6 0xFFFFFFF3 #define V_028354_RASTER_CONFIG_SE_PAIR_XSEL_8_WIDE_TILE 0x00 #define V_028354_RASTER_CONFIG_SE_PAIR_XSEL_16_WIDE_TILE 0x01 #define V_028354_RASTER_CONFIG_SE_PAIR_XSEL_32_WIDE_TILE 0x02 #define V_028354_RASTER_CONFIG_SE_PAIR_XSEL_64_WIDE_TILE 0x03 -#define S_028354_SE_PAIR_YSEL(x) (((unsigned)(x) & 0x03) << 4) -#define G_028354_SE_PAIR_YSEL(x) (((x) >> 4) & 0x03) -#define C_028354_SE_PAIR_YSEL 0xFFFFFFCF +#define S_028354_SE_PAIR_YSEL_GFX6(x) (((unsigned)(x) & 0x03) << 4) +#define G_028354_SE_PAIR_YSEL_GFX6(x) (((x) >> 4) & 0x03) +#define C_028354_SE_PAIR_YSEL_GFX6 0xFFFFFFCF #define V_028354_RASTER_CONFIG_SE_PAIR_YSEL_8_WIDE_TILE 0x00 #define V_028354_RASTER_CONFIG_SE_PAIR_YSEL_16_WIDE_TILE 0x01 #define V_028354_RASTER_CONFIG_SE_PAIR_YSEL_32_WIDE_TILE 0x02 @@ -6704,9 +6704,9 @@ #define R_0287DC_PA_CL_POINT_SIZE 0x0287DC #define R_0287E0_PA_CL_POINT_CULL_RAD 0x0287E0 #define R_0287E4_VGT_DMA_BASE_HI 0x0287E4 -#define S_0287E4_BASE_ADDR(x) (((unsigned)(x) & 0xFF) << 0) -#define G_0287E4_BASE_ADDR(x) (((x) >> 0) & 0xFF) -#define C_0287E4_BASE_ADDR 0xFFFFFF00 +#define S_0287E4_BASE_ADDR_GFX6(x) (((unsigned)(x) & 0xFF) << 0) +#define G_0287E4_BASE_ADDR_GFX6(x) (((x) >> 0) & 0xFF) +#define C_0287E4_BASE_ADDR_GFX6 0xFFFFFF00 #define R_0287E8_VGT_DMA_BASE 0x0287E8 #define R_0287F0_VGT_DRAW_INITIATOR 0x0287F0 #define S_0287F0_SOURCE_SELECT(x) (((unsigned)(x) & 0x03) << 0) @@ -7823,9 +7823,9 @@ #define V_028A90_PIXEL_PIPE_STAT_DUMP 0x39 #define V_028A90_PIXEL_PIPE_STAT_RESET 0x3A /* */ -#define S_028A90_ADDRESS_HI(x) (((unsigned)(x) & 0x1FF) << 18) -#define G_028A90_ADDRESS_HI(x) (((x) >> 18) & 0x1FF) -#define C_028A90_ADDRESS_HI 0xF803FFFF +#define S_028A90_ADDRESS_HI_GFX6(x) (((unsigned)(x) & 0x1FF) << 18) +#define G_028A90_ADDRESS_HI_GFX6(x) (((x) >> 18) & 0x1FF) +#define C_028A90_ADDRESS_HI_GFX6 0xF803FFFF #define S_028A90_EXTENDED_EVENT(x) (((unsigned)(x) & 0x1) << 27) #define G_028A90_EXTENDED_EVENT(x) (((x) >> 27) & 0x1) #define C_028A90_EXTENDED_EVENT 0xF7FFFFFF diff --git a/src/amd/vulkan/radv_image.c b/src/amd/vulkan/radv_image.c index 3997e81acc1..2e03e26ff05 100644 --- a/src/amd/vulkan/radv_image.c +++ b/src/amd/vulkan/radv_image.c @@ -201,7 +201,7 @@ si_set_mutable_tex_desc_fields(struct radv_device *device, state[1] &= C_008F14_BASE_ADDRESS_HI; state[3] &= C_008F1C_TILING_INDEX; - state[4] &= C_008F20_PITCH; + state[4] &= C_008F20_PITCH_GFX6; state[6] &= C_008F28_COMPRESSION_EN; assert(!(va & 255)); @@ -210,7 +210,7 @@ si_set_mutable_tex_desc_fields(struct radv_device *device, state[1] |= S_008F14_BASE_ADDRESS_HI(va >> 40); state[3] |= S_008F1C_TILING_INDEX(si_tile_mode_index(image, base_level, is_stencil)); - state[4] |= S_008F20_PITCH(pitch - 1); + state[4] |= S_008F20_PITCH_GFX6(pitch - 1); if (image->surface.dcc_size && image->surface.level[first_level].dcc_enabled) { state[6] |= S_008F28_COMPRESSION_EN(1); @@ -370,7 +370,7 @@ si_make_texture_descriptor(struct radv_device *device, S_008F1C_TILING_INDEX(image->fmask.tile_mode_index) | S_008F1C_TYPE(radv_tex_dim(image->type, view_type, 1, 0, false)); fmask_state[4] = S_008F20_DEPTH(depth - 1) | - S_008F20_PITCH(image->fmask.pitch_in_pixels - 1); + S_008F20_PITCH_GFX6(image->fmask.pitch_in_pixels - 1); fmask_state[5] = S_008F24_BASE_ARRAY(first_layer) | S_008F24_LAST_ARRAY(last_layer); fmask_state[6] = 0; diff --git a/src/gallium/drivers/radeonsi/si_descriptors.c b/src/gallium/drivers/radeonsi/si_descriptors.c index 2e62725e9ca..c13bc942dc7 100644 --- a/src/gallium/drivers/radeonsi/si_descriptors.c +++ b/src/gallium/drivers/radeonsi/si_descriptors.c @@ -394,14 +394,14 @@ void si_set_mutable_tex_desc_fields(struct r600_texture *tex, state[1] &= C_008F14_BASE_ADDRESS_HI; state[3] &= C_008F1C_TILING_INDEX; - state[4] &= C_008F20_PITCH; + state[4] &= C_008F20_PITCH_GFX6; state[6] &= C_008F28_COMPRESSION_EN; state[0] = va >> 8; state[1] |= S_008F14_BASE_ADDRESS_HI(va >> 40); state[3] |= S_008F1C_TILING_INDEX(si_tile_mode_index(tex, base_level, is_stencil)); - state[4] |= S_008F20_PITCH(pitch - 1); + state[4] |= S_008F20_PITCH_GFX6(pitch - 1); if (tex->dcc_offset && first_level < tex->surface.num_dcc_levels) { state[6] |= S_008F28_COMPRESSION_EN(1); diff --git a/src/gallium/drivers/radeonsi/si_state.c b/src/gallium/drivers/radeonsi/si_state.c index 47d86d7dbdc..b05152f7d30 100644 --- a/src/gallium/drivers/radeonsi/si_state.c +++ b/src/gallium/drivers/radeonsi/si_state.c @@ -3000,7 +3000,7 @@ si_make_texture_descriptor(struct si_screen *screen, S_008F1C_TILING_INDEX(tex->fmask.tile_mode_index) | S_008F1C_TYPE(si_tex_dim(res->target, target, 0)); fmask_state[4] = S_008F20_DEPTH(depth - 1) | - S_008F20_PITCH(tex->fmask.pitch_in_pixels - 1); + S_008F20_PITCH_GFX6(tex->fmask.pitch_in_pixels - 1); fmask_state[5] = S_008F24_BASE_ARRAY(first_layer) | S_008F24_LAST_ARRAY(last_layer); fmask_state[6] = 0; |