diff options
| -rw-r--r-- | src/mesa/drivers/dri/i965/brw_link.cpp | 5 | ||||
| -rw-r--r-- | src/mesa/drivers/dri/i965/intel_extensions.c | 1 |
2 files changed, 6 insertions, 0 deletions
diff --git a/src/mesa/drivers/dri/i965/brw_link.cpp b/src/mesa/drivers/dri/i965/brw_link.cpp index 4159756fc5d..977feb37fc2 100644 --- a/src/mesa/drivers/dri/i965/brw_link.cpp +++ b/src/mesa/drivers/dri/i965/brw_link.cpp @@ -120,6 +120,11 @@ process_glsl_ir(struct brw_context *brw, } lower_instructions(shader->ir, instructions_to_lower); + lower_64bit_integer_instructions(shader->ir, + MUL64 | + DIV64 | + MOD64 | + SIGN64); /* Pre-gen6 HW can only nest if-statements 16 deep. Beyond this, * if-statements need to be flattened. diff --git a/src/mesa/drivers/dri/i965/intel_extensions.c b/src/mesa/drivers/dri/i965/intel_extensions.c index b674b2f494c..f1290bf7b49 100644 --- a/src/mesa/drivers/dri/i965/intel_extensions.c +++ b/src/mesa/drivers/dri/i965/intel_extensions.c @@ -264,6 +264,7 @@ intelInitExtensions(struct gl_context *ctx) } if (brw->gen >= 8) { + ctx->Extensions.ARB_gpu_shader_int64 = true; ctx->Extensions.ARB_ES3_2_compatibility = true; } |