diff options
-rw-r--r-- | src/amd/common/ac_nir_to_llvm.c | 7 | ||||
-rw-r--r-- | src/amd/common/ac_nir_to_llvm.h | 3 | ||||
-rw-r--r-- | src/amd/common/ac_shader_info.c | 37 | ||||
-rw-r--r-- | src/amd/common/ac_shader_info.h | 3 | ||||
-rw-r--r-- | src/amd/vulkan/radv_pipeline.c | 18 |
5 files changed, 52 insertions, 16 deletions
diff --git a/src/amd/common/ac_nir_to_llvm.c b/src/amd/common/ac_nir_to_llvm.c index f1f846caeb5..766d96c5e03 100644 --- a/src/amd/common/ac_nir_to_llvm.c +++ b/src/amd/common/ac_nir_to_llvm.c @@ -6443,15 +6443,12 @@ handle_fs_outputs_post(struct nir_to_llvm_context *ctx) continue; if (i == FRAG_RESULT_DEPTH) { - ctx->shader_info->fs.writes_z = true; depth = ac_to_float(&ctx->ac, LLVMBuildLoad(ctx->builder, ctx->nir->outputs[radeon_llvm_reg_index_soa(i, 0)], "")); } else if (i == FRAG_RESULT_STENCIL) { - ctx->shader_info->fs.writes_stencil = true; stencil = ac_to_float(&ctx->ac, LLVMBuildLoad(ctx->builder, ctx->nir->outputs[radeon_llvm_reg_index_soa(i, 0)], "")); } else if (i == FRAG_RESULT_SAMPLE_MASK) { - ctx->shader_info->fs.writes_sample_mask = true; samplemask = ac_to_float(&ctx->ac, LLVMBuildLoad(ctx->builder, ctx->nir->outputs[radeon_llvm_reg_index_soa(i, 0)], "")); } else { @@ -6460,7 +6457,9 @@ handle_fs_outputs_post(struct nir_to_llvm_context *ctx) values[j] = ac_to_float(&ctx->ac, LLVMBuildLoad(ctx->builder, ctx->nir->outputs[radeon_llvm_reg_index_soa(i, j)], "")); - if (!ctx->shader_info->fs.writes_z && !ctx->shader_info->fs.writes_stencil && !ctx->shader_info->fs.writes_sample_mask) + if (!ctx->shader_info->info.ps.writes_z && + !ctx->shader_info->info.ps.writes_stencil && + !ctx->shader_info->info.ps.writes_sample_mask) last = ctx->output_mask <= ((1ull << (i + 1)) - 1); bool ret = si_export_mrt_color(ctx, values, V_008DFC_SQ_EXP_MRT + (i - FRAG_RESULT_DATA0), last, &color_args[index]); diff --git a/src/amd/common/ac_nir_to_llvm.h b/src/amd/common/ac_nir_to_llvm.h index 9332531ce33..8c925141a09 100644 --- a/src/amd/common/ac_nir_to_llvm.h +++ b/src/amd/common/ac_nir_to_llvm.h @@ -179,9 +179,6 @@ struct ac_shader_variant_info { uint32_t flat_shaded_mask; bool has_pcoord; bool can_discard; - bool writes_z; - bool writes_stencil; - bool writes_sample_mask; bool early_fragment_test; bool prim_id_input; bool layer_input; diff --git a/src/amd/common/ac_shader_info.c b/src/amd/common/ac_shader_info.c index e7132638172..b211da60b32 100644 --- a/src/amd/common/ac_shader_info.c +++ b/src/amd/common/ac_shader_info.c @@ -192,6 +192,40 @@ gather_info_input_decl(const nir_shader *nir, const nir_variable *var, } } +static void +gather_info_output_decl_ps(const nir_shader *nir, const nir_variable *var, + struct ac_shader_info *info) +{ + int idx = var->data.location; + + switch (idx) { + case FRAG_RESULT_DEPTH: + info->ps.writes_z = true; + break; + case FRAG_RESULT_STENCIL: + info->ps.writes_stencil = true; + break; + case FRAG_RESULT_SAMPLE_MASK: + info->ps.writes_sample_mask = true; + break; + default: + break; + } +} + +static void +gather_info_output_decl(const nir_shader *nir, const nir_variable *var, + struct ac_shader_info *info) +{ + switch (nir->info.stage) { + case MESA_SHADER_FRAGMENT: + gather_info_output_decl_ps(nir, var, info); + break; + default: + break; + } +} + void ac_nir_shader_info_pass(const struct nir_shader *nir, const struct ac_nir_compiler_options *options, @@ -209,4 +243,7 @@ ac_nir_shader_info_pass(const struct nir_shader *nir, nir_foreach_block(block, func->impl) { gather_info_block(nir, block, info); } + + nir_foreach_variable(variable, &nir->outputs) + gather_info_output_decl(nir, variable, info); } diff --git a/src/amd/common/ac_shader_info.h b/src/amd/common/ac_shader_info.h index 380c06a8551..7f87582930c 100644 --- a/src/amd/common/ac_shader_info.h +++ b/src/amd/common/ac_shader_info.h @@ -46,6 +46,9 @@ struct ac_shader_info { bool needs_sample_positions; bool uses_input_attachments; bool writes_memory; + bool writes_z; + bool writes_stencil; + bool writes_sample_mask; } ps; struct { bool uses_grid_size; diff --git a/src/amd/vulkan/radv_pipeline.c b/src/amd/vulkan/radv_pipeline.c index 65476373384..8f872e7c149 100644 --- a/src/amd/vulkan/radv_pipeline.c +++ b/src/amd/vulkan/radv_pipeline.c @@ -2810,10 +2810,10 @@ radv_compute_db_shader_control(const struct radv_device *device, else z_order = V_02880C_LATE_Z; - return S_02880C_Z_EXPORT_ENABLE(ps->info.fs.writes_z) | - S_02880C_STENCIL_TEST_VAL_EXPORT_ENABLE(ps->info.fs.writes_stencil) | + return S_02880C_Z_EXPORT_ENABLE(ps->info.info.ps.writes_z) | + S_02880C_STENCIL_TEST_VAL_EXPORT_ENABLE(ps->info.info.ps.writes_stencil) | S_02880C_KILL_ENABLE(!!ps->info.fs.can_discard) | - S_02880C_MASK_EXPORT_ENABLE(ps->info.fs.writes_sample_mask) | + S_02880C_MASK_EXPORT_ENABLE(ps->info.info.ps.writes_sample_mask) | S_02880C_Z_ORDER(z_order) | S_02880C_DEPTH_BEFORE_SHADER(ps->info.fs.early_fragment_test) | S_02880C_EXEC_ON_HIER_FAIL(ps->info.info.ps.writes_memory) | @@ -2853,9 +2853,9 @@ radv_pipeline_generate_fragment_shader(struct radeon_winsys_cs *cs, radeon_set_context_reg(cs, R_0286E0_SPI_BARYC_CNTL, pipeline->graphics.spi_baryc_cntl); radeon_set_context_reg(cs, R_028710_SPI_SHADER_Z_FORMAT, - ac_get_spi_shader_z_format(ps->info.fs.writes_z, - ps->info.fs.writes_stencil, - ps->info.fs.writes_sample_mask)); + ac_get_spi_shader_z_format(ps->info.info.ps.writes_z, + ps->info.info.ps.writes_stencil, + ps->info.info.ps.writes_sample_mask)); if (pipeline->device->dfsm_allowed) { /* optimise this? */ @@ -3183,9 +3183,9 @@ radv_pipeline_init(struct radv_pipeline *pipeline, */ struct radv_shader_variant *ps = pipeline->shaders[MESA_SHADER_FRAGMENT]; if (!blend.spi_shader_col_format) { - if (!ps->info.fs.writes_z && - !ps->info.fs.writes_stencil && - !ps->info.fs.writes_sample_mask) + if (!ps->info.info.ps.writes_z && + !ps->info.info.ps.writes_stencil && + !ps->info.info.ps.writes_sample_mask) blend.spi_shader_col_format = V_028714_SPI_SHADER_32_R; } |