diff options
| -rw-r--r-- | src/mesa/drivers/dri/r600/r600_emit.h | 19 | ||||
| -rw-r--r-- | src/mesa/drivers/dri/radeon/radeon_cmdbuf.h | 106 |
2 files changed, 106 insertions, 19 deletions
diff --git a/src/mesa/drivers/dri/r600/r600_emit.h b/src/mesa/drivers/dri/r600/r600_emit.h index bf106a8ad24..3e1cf1ff5f6 100644 --- a/src/mesa/drivers/dri/r600/r600_emit.h +++ b/src/mesa/drivers/dri/r600/r600_emit.h @@ -47,21 +47,10 @@ static INLINE uint32_t cmdpacket0(struct radeon_screen *rscrn, int reg, int count) { - if (!rscrn->kernel_mm) { - drm_r300_cmd_header_t cmd; - - cmd.u = 0; - cmd.packet0.cmd_type = R300_CMD_PACKET0; - cmd.packet0.count = count; - cmd.packet0.reghi = ((unsigned int)reg & 0xFF00) >> 8; - cmd.packet0.reglo = ((unsigned int)reg & 0x00FF); - - return cmd.u; - } - if (count) { - return CP_PACKET0(reg, count - 1); - } - return CP_PACKET2; + if (count) { + return CP_PACKET0(reg, count - 1); + } + return CP_PACKET2; } static INLINE uint32_t cmdvpu(struct radeon_screen *rscrn, int addr, int count) diff --git a/src/mesa/drivers/dri/radeon/radeon_cmdbuf.h b/src/mesa/drivers/dri/radeon/radeon_cmdbuf.h index 4b5116c4741..851b4884336 100644 --- a/src/mesa/drivers/dri/radeon/radeon_cmdbuf.h +++ b/src/mesa/drivers/dri/radeon/radeon_cmdbuf.h @@ -38,11 +38,68 @@ void rcommonBeginBatch(radeonContextPtr rmesa, #define RADEON_CP_PACKET3_CNTL_BITBLT_MULTI 0xC0009B00 #define RADEON_CP_PACKET3_CNTL_TRANS_BITBLT 0xC0009C00 +/* r6xx/r7xx packet 3 type offsets */ +#define R600_SET_CONFIG_REG_OFFSET 0x00008000 +#define R600_SET_CONFIG_REG_END 0x0000ac00 +#define R600_SET_CONTEXT_REG_OFFSET 0x00028000 +#define R600_SET_CONTEXT_REG_END 0x00029000 +#define R600_SET_ALU_CONST_OFFSET 0x00030000 +#define R600_SET_ALU_CONST_END 0x00032000 +#define R600_SET_RESOURCE_OFFSET 0x00038000 +#define R600_SET_RESOURCE_END 0x0003c000 +#define R600_SET_SAMPLER_OFFSET 0x0003c000 +#define R600_SET_SAMPLER_END 0x0003cff0 +#define R600_SET_CTL_CONST_OFFSET 0x0003cff0 +#define R600_SET_CTL_CONST_END 0x0003e200 +#define R600_SET_LOOP_CONST_OFFSET 0x0003e200 +#define R600_SET_LOOP_CONST_END 0x0003e380 +#define R600_SET_BOOL_CONST_OFFSET 0x0003e380 +#define R600_SET_BOOL_CONST_END 0x00040000 + +/* r6xx/r7xx packet 3 types */ +#define R600_IT_INDIRECT_BUFFER_END 0x00001700 +#define R600_IT_SET_PREDICATION 0x00002000 +#define R600_IT_REG_RMW 0x00002100 +#define R600_IT_COND_EXEC 0x00002200 +#define R600_IT_PRED_EXEC 0x00002300 +#define R600_IT_START_3D_CMDBUF 0x00002400 +#define R600_IT_DRAW_INDEX_2 0x00002700 +#define R600_IT_CONTEXT_CONTROL 0x00002800 +#define R600_IT_DRAW_INDEX_IMMD_BE 0x00002900 +#define R600_IT_INDEX_TYPE 0x00002A00 +#define R600_IT_DRAW_INDEX 0x00002B00 +#define R600_IT_DRAW_INDEX_AUTO 0x00002D00 +#define R600_IT_DRAW_INDEX_IMMD 0x00002E00 +#define R600_IT_NUM_INSTANCES 0x00002F00 +#define R600_IT_STRMOUT_BUFFER_UPDATE 0x00003400 +#define R600_IT_INDIRECT_BUFFER_MP 0x00003800 +#define R600_IT_MEM_SEMAPHORE 0x00003900 +#define R600_IT_MPEG_INDEX 0x00003A00 +#define R600_IT_WAIT_REG_MEM 0x00003C00 +#define R600_IT_MEM_WRITE 0x00003D00 +#define R600_IT_INDIRECT_BUFFER 0x00003200 +#define R600_IT_CP_INTERRUPT 0x00004000 +#define R600_IT_SURFACE_SYNC 0x00004300 +#define R600_IT_ME_INITIALIZE 0x00004400 +#define R600_IT_COND_WRITE 0x00004500 +#define R600_IT_EVENT_WRITE 0x00004600 +#define R600_IT_EVENT_WRITE_EOP 0x00004700 +#define R600_IT_ONE_REG_WRITE 0x00005700 +#define R600_IT_SET_CONFIG_REG 0x00006800 +#define R600_IT_SET_CONTEXT_REG 0x00006900 +#define R600_IT_SET_ALU_CONST 0x00006A00 +#define R600_IT_SET_BOOL_CONST 0x00006B00 +#define R600_IT_SET_LOOP_CONST 0x00006C00 +#define R600_IT_SET_RESOURCE 0x00006D00 +#define R600_IT_SET_SAMPLER 0x00006E00 +#define R600_IT_SET_CTL_CONST 0x00006F00 +#define R600_IT_SURFACE_BASE_UPDATE 0x00007300 + + #define CP_PACKET2 (2 << 30) #define CP_PACKET0(reg, n) (RADEON_CP_PACKET0 | ((n)<<16) | ((reg)>>2)) #define CP_PACKET0_ONE(reg, n) (RADEON_CP_PACKET0 | RADEON_CP_PACKET0_ONE_REG_WR | ((n)<<16) | ((reg)>>2)) -#define CP_PACKET3( pkt, n ) \ - (RADEON_CP_PACKET3 | (pkt) | ((n) << 16)) +#define CP_PACKET3(pkt, n) (RADEON_CP_PACKET3 | (pkt) | ((n) << 16)) /** * Every function writing to the command buffer needs to declare this @@ -125,12 +182,53 @@ void rcommonBeginBatch(radeonContextPtr rmesa, /** Continuous register range write to command buffer; requires 1 dword, * expects count dwords afterwards for register contents. */ #define OUT_BATCH_REGSEQ(reg, count) \ - OUT_BATCH(cmdpacket0(b_l_rmesa->radeonScreen, (reg), (count))); + OUT_BATCH(cmdpacket0(b_l_rmesa->radeonScreen, (reg), (count))) /** Write a 32 bit float to the ring; requires 1 dword. */ #define OUT_BATCH_FLOAT32(f) \ - OUT_BATCH(radeonPackFloat32((f))); + OUT_BATCH(radeonPackFloat32((f))) + +/* R600/R700 */ +#define R600_OUT_BATCH_REGS(reg, num) \ +do { \ + if ((reg) >= R600_SET_CONFIG_REG_OFFSET && (reg) < R600_SET_CONFIG_REG_END) { \ + OUT_BATCH(CP_PACKET3(R600_IT_SET_CONFIG_REG, (num))); \ + OUT_BATCH(((reg) - R600_SET_CONFIG_REG_OFFSET) >> 2); \ + } else if ((reg) >= R600_SET_CONTEXT_REG_OFFSET && (reg) < R600_SET_CONTEXT_REG_END) { \ + OUT_BATCH(CP_PACKET3(R600_IT_SET_CONTEXT_REG, (num))); \ + OUT_BATCH(((reg) - R600_SET_CONTEXT_REG_OFFSET) >> 2); \ + } else if ((reg) >= R600_SET_ALU_CONST_OFFSET && (reg) < R600_SET_ALU_CONST_END) { \ + OUT_BATCH(CP_PACKET3(R600_IT_SET_ALU_CONST, (num))); \ + OUT_BATCH(((reg) - R600_SET_ALU_CONST_OFFSET) >> 2); \ + } else if ((reg) >= R600_SET_RESOURCE_OFFSET && (reg) < R600_SET_RESOURCE_END) { \ + OUT_BATCH(CP_PACKET3(R600_IT_SET_RESOURCE, (num))); \ + OUT_BATCH(((reg) - R600_SET_RESOURCE_OFFSET) >> 2); \ + } else if ((reg) >= R600_SET_SAMPLER_OFFSET && (reg) < R600_SET_SAMPLER_END) { \ + OUT_BATCH(CP_PACKET3(R600_IT_SET_SAMPLER, (num))); \ + OUT_BATCH(((reg) - R600_SET_SAMPLER_OFFSET) >> 2); \ + } else if ((reg) >= R600_SET_CTL_CONST_OFFSET && (reg) < R600_SET_CTL_CONST_END) { \ + OUT_BATCH(CP_PACKET3(R600_IT_SET_CTL_CONST, (num))); \ + OUT_BATCH(((reg) - R600_SET_CTL_CONST_OFFSET) >> 2); \ + } else if ((reg) >= R600_SET_LOOP_CONST_OFFSET && (reg) < R600_SET_LOOP_CONST_END) { \ + OUT_BATCH(CP_PACKET3(R600_IT_SET_LOOP_CONST, (num))); \ + OUT_BATCH(((reg) - R600_SET_LOOP_CONST_OFFSET) >> 2); \ + } else if ((reg) >= R600_SET_BOOL_CONST_OFFSET && (reg) < R600_SET_BOOL_CONST_END) { \ + OUT_BATCH(CP_PACKET3(R600_IT_SET_BOOL_CONST, (num))); \ + OUT_BATCH(((reg) - R600_SET_BOOL_CONST_OFFSET) >> 2); \ + } else { \ + OUT_BATCH(cmdpacket0(b_l_rmesa->radeonScreen, (reg), (num))); \ + } \ +} while (0) + +/** Single register write to command buffer; requires 3 dwords for most things. */ +#define R600_OUT_BATCH_REGVAL(reg, val) \ + R600_OUT_BATCH_REGS((reg), 1); \ + OUT_BATCH((val)) +/** Continuous register range write to command buffer; requires 1 dword, + * expects count dwords afterwards for register contents. */ +#define R600_OUT_BATCH_REGSEQ(reg, count) \ + R600_OUT_BATCH_REGS((reg), (count)) /* Fire the buffered vertices no matter what. */ |