diff options
| -rw-r--r-- | src/mesa/drivers/dri/i965/brw_vec4_nir.cpp | 26 |
1 files changed, 26 insertions, 0 deletions
diff --git a/src/mesa/drivers/dri/i965/brw_vec4_nir.cpp b/src/mesa/drivers/dri/i965/brw_vec4_nir.cpp index c681ae438ef..0db2291d84e 100644 --- a/src/mesa/drivers/dri/i965/brw_vec4_nir.cpp +++ b/src/mesa/drivers/dri/i965/brw_vec4_nir.cpp @@ -538,6 +538,32 @@ vec4_visitor::nir_emit_intrinsic(nir_intrinsic_instr *instr) break; } + case nir_intrinsic_get_buffer_size: { + nir_const_value *const_uniform_block = nir_src_as_const_value(instr->src[0]); + unsigned ubo_index = const_uniform_block ? const_uniform_block->u[0] : 0; + + assert(shader->base.UniformBlocks[ubo_index].IsShaderStorage); + + src_reg surf_index = src_reg(prog_data->base.binding_table.ubo_start + + ubo_index); + dst_reg result_dst = get_nir_dest(instr->dest); + vec4_instruction *inst = new(mem_ctx) + vec4_instruction(VS_OPCODE_GET_BUFFER_SIZE, result_dst); + + inst->base_mrf = 2; + inst->mlen = 1; /* always at least one */ + inst->src[1] = src_reg(surf_index); + + /* MRF for the first parameter */ + src_reg lod = src_reg(0); + int param_base = inst->base_mrf; + int writemask = WRITEMASK_X; + emit(MOV(dst_reg(MRF, param_base, glsl_type::int_type, writemask), lod)); + + emit(inst); + break; + } + case nir_intrinsic_load_vertex_id: unreachable("should be lowered by lower_vertex_id()"); |