diff options
| -rw-r--r-- | src/amd/common/ac_gpu_info.c | 3 | ||||
| -rw-r--r-- | src/amd/common/ac_gpu_info.h | 1 | ||||
| -rw-r--r-- | src/gallium/drivers/radeonsi/si_get.c | 6 | ||||
| -rw-r--r-- | src/gallium/winsys/radeon/drm/radeon_drm_winsys.c | 3 |
4 files changed, 8 insertions, 5 deletions
diff --git a/src/amd/common/ac_gpu_info.c b/src/amd/common/ac_gpu_info.c index 5a395772460..0451b8fb987 100644 --- a/src/amd/common/ac_gpu_info.c +++ b/src/amd/common/ac_gpu_info.c @@ -328,6 +328,8 @@ bool ac_query_gpu_info(int fd, amdgpu_device_handle dev, info->kernel_flushes_tc_l2_after_ib = info->chip_class != VI || info->drm_minor >= 2; info->has_indirect_compute_dispatch = true; + /* SI doesn't support unaligned loads. */ + info->has_unaligned_shader_loads = info->chip_class != SI; info->num_render_backends = amdinfo->rb_pipes; /* The value returned by the kernel driver was wrong. */ @@ -485,6 +487,7 @@ void ac_print_gpu_info(struct radeon_info *info) printf(" has_format_bc1_through_bc7 = %u\n", info->has_format_bc1_through_bc7); printf(" kernel_flushes_tc_l2_after_ib = %u\n", info->kernel_flushes_tc_l2_after_ib); printf(" has_indirect_compute_dispatch = %u\n", info->has_indirect_compute_dispatch); + printf(" has_unaligned_shader_loads = %u\n", info->has_unaligned_shader_loads); printf("Shader core info:\n"); printf(" max_shader_clock = %i\n", info->max_shader_clock); diff --git a/src/amd/common/ac_gpu_info.h b/src/amd/common/ac_gpu_info.h index d5d10c60102..e95dcbd906c 100644 --- a/src/amd/common/ac_gpu_info.h +++ b/src/amd/common/ac_gpu_info.h @@ -106,6 +106,7 @@ struct radeon_info { bool has_format_bc1_through_bc7; bool kernel_flushes_tc_l2_after_ib; bool has_indirect_compute_dispatch; + bool has_unaligned_shader_loads; /* Shader cores. */ uint32_t r600_max_quad_pipes; /* wave size / 16 */ diff --git a/src/gallium/drivers/radeonsi/si_get.c b/src/gallium/drivers/radeonsi/si_get.c index 3feb1ae7823..d2bee21a1fe 100644 --- a/src/gallium/drivers/radeonsi/si_get.c +++ b/src/gallium/drivers/radeonsi/si_get.c @@ -226,11 +226,7 @@ static int si_get_param(struct pipe_screen *pscreen, enum pipe_cap param) case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY: case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY: case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY: - /* SI doesn't support unaligned loads. - * CIK needs DRM 2.50.0 on radeon. */ - return sscreen->info.chip_class == SI || - (sscreen->info.drm_major == 2 && - sscreen->info.drm_minor < 50); + return !sscreen->info.has_unaligned_shader_loads; case PIPE_CAP_SPARSE_BUFFER_PAGE_SIZE: /* TODO: GFX9 hangs. */ diff --git a/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c b/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c index 129d4f46f5b..7a55fca3020 100644 --- a/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c +++ b/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c @@ -544,6 +544,9 @@ static bool do_winsys_init(struct radeon_drm_winsys *ws) ws->info.has_indirect_compute_dispatch = ws->info.chip_class == CIK || (ws->info.chip_class == SI && ws->info.drm_minor >= 45); + /* SI doesn't support unaligned loads. */ + ws->info.has_unaligned_shader_loads = ws->info.chip_class == CIK && + ws->info.drm_minor >= 50; ws->check_vm = strstr(debug_get_option("R600_DEBUG", ""), "check_vm") != NULL; |