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-rw-r--r--src/amd/vulkan/radv_pipeline.c4
-rw-r--r--src/broadcom/compiler/vir.c2
-rw-r--r--src/compiler/Makefile.sources1
-rw-r--r--src/compiler/nir/meson.build1
-rw-r--r--src/compiler/nir/nir.h1
-rw-r--r--src/compiler/nir/nir_lower_bool_to_int32.c160
-rw-r--r--src/freedreno/ir3/ir3_context.c1
-rw-r--r--src/gallium/drivers/radeonsi/si_shader_nir.c2
-rw-r--r--src/gallium/drivers/vc4/vc4_program.c2
-rw-r--r--src/intel/compiler/brw_nir.c2
10 files changed, 176 insertions, 0 deletions
diff --git a/src/amd/vulkan/radv_pipeline.c b/src/amd/vulkan/radv_pipeline.c
index 92c35b2e509..3561d17aaba 100644
--- a/src/amd/vulkan/radv_pipeline.c
+++ b/src/amd/vulkan/radv_pipeline.c
@@ -2087,6 +2087,10 @@ void radv_create_shaders(struct radv_pipeline *pipeline,
radv_link_shaders(pipeline, nir);
for (int i = 0; i < MESA_SHADER_STAGES; ++i) {
+ if (nir[i]) {
+ NIR_PASS_V(nir[i], nir_lower_bool_to_int32);
+ }
+
if (radv_can_dump_shader(device, modules[i], false))
nir_print_shader(nir[i], stderr);
}
diff --git a/src/broadcom/compiler/vir.c b/src/broadcom/compiler/vir.c
index 518aace991a..9bec5e54e13 100644
--- a/src/broadcom/compiler/vir.c
+++ b/src/broadcom/compiler/vir.c
@@ -756,6 +756,7 @@ uint64_t *v3d_compile_vs(const struct v3d_compiler *compiler,
v3d_lower_nir_late(c);
v3d_optimize_nir(c->s);
+ NIR_PASS_V(c->s, nir_lower_bool_to_int32);
NIR_PASS_V(c->s, nir_convert_from_ssa, true);
v3d_nir_to_vir(c);
@@ -907,6 +908,7 @@ uint64_t *v3d_compile_fs(const struct v3d_compiler *compiler,
v3d_lower_nir_late(c);
v3d_optimize_nir(c->s);
+ NIR_PASS_V(c->s, nir_lower_bool_to_int32);
NIR_PASS_V(c->s, nir_convert_from_ssa, true);
v3d_nir_to_vir(c);
diff --git a/src/compiler/Makefile.sources b/src/compiler/Makefile.sources
index 53c6da45c1e..ef47bdb33bf 100644
--- a/src/compiler/Makefile.sources
+++ b/src/compiler/Makefile.sources
@@ -231,6 +231,7 @@ NIR_FILES = \
nir/nir_lower_atomics_to_ssbo.c \
nir/nir_lower_bitmap.c \
nir/nir_lower_bit_size.c \
+ nir/nir_lower_bool_to_int32.c \
nir/nir_lower_clamp_color_outputs.c \
nir/nir_lower_clip.c \
nir/nir_lower_clip_cull_distance_arrays.c \
diff --git a/src/compiler/nir/meson.build b/src/compiler/nir/meson.build
index 5eb1df2a68f..e252f64539e 100644
--- a/src/compiler/nir/meson.build
+++ b/src/compiler/nir/meson.build
@@ -114,6 +114,7 @@ files_libnir = files(
'nir_lower_alpha_test.c',
'nir_lower_atomics_to_ssbo.c',
'nir_lower_bitmap.c',
+ 'nir_lower_bool_to_int32.c',
'nir_lower_clamp_color_outputs.c',
'nir_lower_clip.c',
'nir_lower_clip_cull_distance_arrays.c',
diff --git a/src/compiler/nir/nir.h b/src/compiler/nir/nir.h
index dca1c80d6e2..24dee98ef51 100644
--- a/src/compiler/nir/nir.h
+++ b/src/compiler/nir/nir.h
@@ -2905,6 +2905,7 @@ void nir_lower_alpha_test(nir_shader *shader, enum compare_func func,
bool alpha_to_one);
bool nir_lower_alu(nir_shader *shader);
bool nir_lower_alu_to_scalar(nir_shader *shader);
+bool nir_lower_bool_to_int32(nir_shader *shader);
bool nir_lower_load_const_to_scalar(nir_shader *shader);
bool nir_lower_read_invocation_to_scalar(nir_shader *shader);
bool nir_lower_phis_to_scalar(nir_shader *shader);
diff --git a/src/compiler/nir/nir_lower_bool_to_int32.c b/src/compiler/nir/nir_lower_bool_to_int32.c
new file mode 100644
index 00000000000..064b27b9025
--- /dev/null
+++ b/src/compiler/nir/nir_lower_bool_to_int32.c
@@ -0,0 +1,160 @@
+/*
+ * Copyright © 2018 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ */
+
+#include "nir.h"
+
+static bool
+assert_ssa_def_is_not_1bit(nir_ssa_def *def, UNUSED void *unused)
+{
+ assert(def->bit_size > 1);
+ return true;
+}
+
+static bool
+rewrite_1bit_ssa_def_to_32bit(nir_ssa_def *def, void *_progress)
+{
+ bool *progress = _progress;
+ if (def->bit_size == 1) {
+ def->bit_size = 32;
+ *progress = true;
+ }
+ return true;
+}
+
+static bool
+lower_alu_instr(nir_alu_instr *alu)
+{
+ const nir_op_info *op_info = &nir_op_infos[alu->op];
+
+ switch (alu->op) {
+ case nir_op_imov:
+ case nir_op_vec2:
+ case nir_op_vec3:
+ case nir_op_vec4:
+ case nir_op_inot:
+ case nir_op_iand:
+ case nir_op_ior:
+ case nir_op_ixor:
+ /* These we expect to have booleans but the opcode doesn't change */
+ break;
+
+ case nir_op_f2b1: alu->op = nir_op_f2b32; break;
+ case nir_op_i2b1: alu->op = nir_op_i2b32; break;
+
+ case nir_op_flt: alu->op = nir_op_flt32; break;
+ case nir_op_fge: alu->op = nir_op_fge32; break;
+ case nir_op_feq: alu->op = nir_op_feq32; break;
+ case nir_op_fne: alu->op = nir_op_fne32; break;
+ case nir_op_ilt: alu->op = nir_op_ilt32; break;
+ case nir_op_ige: alu->op = nir_op_ige32; break;
+ case nir_op_ieq: alu->op = nir_op_ieq32; break;
+ case nir_op_ine: alu->op = nir_op_ine32; break;
+ case nir_op_ult: alu->op = nir_op_ult32; break;
+ case nir_op_uge: alu->op = nir_op_uge32; break;
+
+ case nir_op_ball_fequal2: alu->op = nir_op_b32all_fequal2; break;
+ case nir_op_ball_fequal3: alu->op = nir_op_b32all_fequal3; break;
+ case nir_op_ball_fequal4: alu->op = nir_op_b32all_fequal4; break;
+ case nir_op_bany_fnequal2: alu->op = nir_op_b32any_fnequal2; break;
+ case nir_op_bany_fnequal3: alu->op = nir_op_b32any_fnequal3; break;
+ case nir_op_bany_fnequal4: alu->op = nir_op_b32any_fnequal4; break;
+ case nir_op_ball_iequal2: alu->op = nir_op_b32all_iequal2; break;
+ case nir_op_ball_iequal3: alu->op = nir_op_b32all_iequal3; break;
+ case nir_op_ball_iequal4: alu->op = nir_op_b32all_iequal4; break;
+ case nir_op_bany_inequal2: alu->op = nir_op_b32any_inequal2; break;
+ case nir_op_bany_inequal3: alu->op = nir_op_b32any_inequal3; break;
+ case nir_op_bany_inequal4: alu->op = nir_op_b32any_inequal4; break;
+
+ case nir_op_bcsel: alu->op = nir_op_b32csel; break;
+
+ default:
+ assert(alu->dest.dest.ssa.bit_size > 1);
+ for (unsigned i = 0; i < op_info->num_inputs; i++)
+ assert(alu->src[i].src.ssa->bit_size > 1);
+ return false;
+ }
+
+ if (alu->dest.dest.ssa.bit_size == 1)
+ alu->dest.dest.ssa.bit_size = 32;
+
+ return true;
+}
+
+static bool
+nir_lower_bool_to_int32_impl(nir_function_impl *impl)
+{
+ bool progress = false;
+
+ nir_foreach_block(block, impl) {
+ nir_foreach_instr_safe(instr, block) {
+ switch (instr->type) {
+ case nir_instr_type_alu:
+ progress |= lower_alu_instr(nir_instr_as_alu(instr));
+ break;
+
+ case nir_instr_type_load_const: {
+ nir_load_const_instr *load = nir_instr_as_load_const(instr);
+ if (load->def.bit_size == 1) {
+ nir_const_value value = load->value;
+ for (unsigned i = 0; i < load->def.num_components; i++)
+ load->value.u32[i] = value.b[i] ? NIR_TRUE : NIR_FALSE;
+ load->def.bit_size = 32;
+ progress = true;
+ }
+ break;
+ }
+
+ case nir_instr_type_intrinsic:
+ case nir_instr_type_ssa_undef:
+ case nir_instr_type_phi:
+ case nir_instr_type_tex:
+ nir_foreach_ssa_def(instr, rewrite_1bit_ssa_def_to_32bit,
+ &progress);
+ break;
+
+ default:
+ nir_foreach_ssa_def(instr, assert_ssa_def_is_not_1bit, NULL);
+ }
+ }
+ }
+
+ if (progress) {
+ nir_metadata_preserve(impl, nir_metadata_block_index |
+ nir_metadata_dominance);
+ }
+
+ return progress;
+}
+
+bool
+nir_lower_bool_to_int32(nir_shader *shader)
+{
+ bool progress = false;
+
+ nir_foreach_function(function, shader) {
+ if (function->impl && nir_lower_bool_to_int32_impl(function->impl))
+ progress = true;
+ }
+
+ return progress;
+}
diff --git a/src/freedreno/ir3/ir3_context.c b/src/freedreno/ir3/ir3_context.c
index f93c4d5f77c..bba41377525 100644
--- a/src/freedreno/ir3/ir3_context.c
+++ b/src/freedreno/ir3/ir3_context.c
@@ -77,6 +77,7 @@ ir3_context_init(struct ir3_compiler *compiler,
/* this needs to be the last pass run, so do this here instead of
* in ir3_optimize_nir():
*/
+ NIR_PASS_V(ctx->s, nir_lower_bool_to_int32);
NIR_PASS_V(ctx->s, nir_lower_locals_to_regs);
NIR_PASS_V(ctx->s, nir_convert_from_ssa, true);
diff --git a/src/gallium/drivers/radeonsi/si_shader_nir.c b/src/gallium/drivers/radeonsi/si_shader_nir.c
index e7ba282b075..01559866274 100644
--- a/src/gallium/drivers/radeonsi/si_shader_nir.c
+++ b/src/gallium/drivers/radeonsi/si_shader_nir.c
@@ -853,6 +853,8 @@ si_lower_nir(struct si_shader_selector* sel)
NIR_PASS(progress, sel->nir, nir_opt_loop_unroll, 0);
}
} while (progress);
+
+ NIR_PASS_V(sel->nir, nir_lower_bool_to_int32);
}
static void declare_nir_input_vs(struct si_shader_context *ctx,
diff --git a/src/gallium/drivers/vc4/vc4_program.c b/src/gallium/drivers/vc4/vc4_program.c
index b85df172892..7053c66723b 100644
--- a/src/gallium/drivers/vc4/vc4_program.c
+++ b/src/gallium/drivers/vc4/vc4_program.c
@@ -2385,6 +2385,8 @@ vc4_shader_ntq(struct vc4_context *vc4, enum qstage stage,
vc4_optimize_nir(c->s);
+ NIR_PASS_V(c->s, nir_lower_bool_to_int32);
+
NIR_PASS_V(c->s, nir_convert_from_ssa, true);
if (vc4_debug & VC4_DEBUG_SHADERDB) {
diff --git a/src/intel/compiler/brw_nir.c b/src/intel/compiler/brw_nir.c
index 44a720c6506..594edde5413 100644
--- a/src/intel/compiler/brw_nir.c
+++ b/src/intel/compiler/brw_nir.c
@@ -822,6 +822,8 @@ brw_postprocess_nir(nir_shader *nir, const struct brw_compiler *compiler,
nir_print_shader(nir, stderr);
}
+ OPT(nir_lower_bool_to_int32);
+
OPT(nir_convert_from_ssa, true);
if (!is_scalar) {
generated by cgit v1.2.3 (git 2.39.1) at 2024-12-02 14:07:20 +0000