diff options
| author | Samuel Pitoiset <[email protected]> | 2020-04-04 10:07:51 +0200 |
|---|---|---|
| committer | Marge Bot <[email protected]> | 2020-04-13 11:51:17 +0000 |
| commit | fc1068de0d124b746cc85b58564810c5453feee3 (patch) | |
| tree | 61881e7fb3c0a9850b2efba618ce2a3369046c06 /src | |
| parent | 4cfaef68d7de7959f6adeaec53077a630b603184 (diff) | |
aco: fix nir_op_pack_32_2x16_split if one operand is a constant
Because 16-bit constants are represented with the s1 RegClass, we
have to extract the low half.
Signed-off-by: Samuel Pitoiset <[email protected]>
Reviewed-by: Daniel Schürmann <[email protected]>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4509>
Diffstat (limited to 'src')
| -rw-r--r-- | src/amd/compiler/aco_instruction_selection.cpp | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/src/amd/compiler/aco_instruction_selection.cpp b/src/amd/compiler/aco_instruction_selection.cpp index f713a761008..bc973a05e5a 100644 --- a/src/amd/compiler/aco_instruction_selection.cpp +++ b/src/amd/compiler/aco_instruction_selection.cpp @@ -2771,6 +2771,8 @@ void visit_alu_instr(isel_context *ctx, nir_alu_instr *instr) Temp src0 = get_alu_src(ctx, instr->src[0]); Temp src1 = get_alu_src(ctx, instr->src[1]); if (dst.regClass() == v1) { + src0 = emit_extract_vector(ctx, src0, 0, v2b); + src1 = emit_extract_vector(ctx, src1, 0, v2b); bld.pseudo(aco_opcode::p_create_vector, Definition(dst), src0, src1); } else { src0 = bld.sop2(aco_opcode::s_and_b32, bld.def(s1), bld.def(s1, scc), src0, Operand(0xFFFFu)); |