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authorTom Stellard <[email protected]>2012-08-31 09:59:00 -0400
committerTom Stellard <[email protected]>2012-08-31 12:54:58 -0400
commitee45dec7c4a673cfa3ce158bdfb7df8aa4282f92 (patch)
tree665fe8c9955cd0d4d6c6d4396fe2082a5253952f /src
parentfc8b4765d001fd214abcffc85b14bf527b0fd5be (diff)
radeon/llvm: Add support for RCP instruction on SI
Diffstat (limited to 'src')
-rw-r--r--src/gallium/drivers/radeon/SIInstructions.td4
1 files changed, 3 insertions, 1 deletions
diff --git a/src/gallium/drivers/radeon/SIInstructions.td b/src/gallium/drivers/radeon/SIInstructions.td
index 6653a66672b..7802ec6cb54 100644
--- a/src/gallium/drivers/radeon/SIInstructions.td
+++ b/src/gallium/drivers/radeon/SIInstructions.td
@@ -532,7 +532,9 @@ defm V_LOG_CLAMP_F32 : VOP1_32 <0x00000026, "V_LOG_CLAMP_F32", []>;
defm V_LOG_F32 : VOP1_32 <0x00000027, "V_LOG_F32", []>;
defm V_RCP_CLAMP_F32 : VOP1_32 <0x00000028, "V_RCP_CLAMP_F32", []>;
defm V_RCP_LEGACY_F32 : VOP1_32 <0x00000029, "V_RCP_LEGACY_F32", []>;
-defm V_RCP_F32 : VOP1_32 <0x0000002a, "V_RCP_F32", []>;
+defm V_RCP_F32 : VOP1_32 <0x0000002a, "V_RCP_F32",
+ [(set VReg_32:$dst, (int_AMDGPU_rcp AllReg_32:$src0))]
+>;
defm V_RCP_IFLAG_F32 : VOP1_32 <0x0000002b, "V_RCP_IFLAG_F32", []>;
defm V_RSQ_CLAMP_F32 : VOP1_32 <0x0000002c, "V_RSQ_CLAMP_F32", []>;
defm V_RSQ_LEGACY_F32 : VOP1_32 <