diff options
| author | Jason Ekstrand <[email protected]> | 2017-06-14 22:28:25 -0700 |
|---|---|---|
| committer | Kenneth Graunke <[email protected]> | 2017-10-12 19:58:40 -0700 |
| commit | d9ed4f6c32b4cb1d7e0f41b1f342c336e70c0af4 (patch) | |
| tree | 97d232d54ff8a56601d00c44b0b8f6639678317f /src | |
| parent | 45991479a3f83501652240a66424a7b64a93e4d7 (diff) | |
i965/barrier: Do the correct flushes for framebuffer access
Framebuffer access includes framebuffer reads so we need to invalidate
the texture cache. We do not, however, need to flush the depth cache
because you cannot do bind a depth texture as an image.
Reviewed-by: Topi Pohjolainen <[email protected]>
Reviewed-by: Kenneth Graunke <[email protected]>
Diffstat (limited to 'src')
| -rw-r--r-- | src/mesa/drivers/dri/i965/brw_program.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/mesa/drivers/dri/i965/brw_program.c b/src/mesa/drivers/dri/i965/brw_program.c index 3743fa9b5eb..c11ac871e58 100644 --- a/src/mesa/drivers/dri/i965/brw_program.c +++ b/src/mesa/drivers/dri/i965/brw_program.c @@ -274,7 +274,7 @@ brw_memory_barrier(struct gl_context *ctx, GLbitfield barriers) PIPE_CONTROL_RENDER_TARGET_FLUSH); if (barriers & GL_FRAMEBUFFER_BARRIER_BIT) - bits |= (PIPE_CONTROL_DEPTH_CACHE_FLUSH | + bits |= (PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE | PIPE_CONTROL_RENDER_TARGET_FLUSH); /* Typed surface messages are handled by the render cache on IVB, so we |