diff options
| author | Marek Olšák <[email protected]> | 2020-03-10 20:44:03 -0400 |
|---|---|---|
| committer | Marge Bot <[email protected]> | 2020-03-12 17:27:23 +0000 |
| commit | bf5b65d0fdfc49a6c2cbdc10fc4b6990f992deea (patch) | |
| tree | cf0092b49fde0e3abae9b2c5a28ef7a653e650d7 /src | |
| parent | e6e97ea92e07b78494f08197d9d5d1f35e1c0b60 (diff) | |
radeonsi/gfx10: cache metadata in L2 on small chips
same as PAL.
Acked-by: Pierre-Eric Pelloux-Prayer <[email protected]>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4143>
Diffstat (limited to 'src')
| -rw-r--r-- | src/gallium/drivers/radeonsi/si_state.c | 27 |
1 files changed, 19 insertions, 8 deletions
diff --git a/src/gallium/drivers/radeonsi/si_state.c b/src/gallium/drivers/radeonsi/si_state.c index 34b903c6fc0..04d514e2174 100644 --- a/src/gallium/drivers/radeonsi/si_state.c +++ b/src/gallium/drivers/radeonsi/si_state.c @@ -5633,23 +5633,34 @@ static void si_init_config(struct si_context *sctx) sscreen->info.pa_sc_tile_steering_override); } + /* Enable CMASK/FMASK/HTILE/DCC caching in L2 for small chips. */ + unsigned meta_write_policy, meta_read_policy; + /* TODO: investigate whether LRU improves performance on other chips too */ + if (sscreen->info.num_render_backends <= 4) { + meta_write_policy = V_02807C_CACHE_LRU_WR; /* cache writes */ + meta_read_policy = V_02807C_CACHE_LRU_RD; /* cache reads */ + } else { + meta_write_policy = V_02807C_CACHE_STREAM_WR; /* write combine */ + meta_read_policy = V_02807C_CACHE_NOA_RD; /* don't cache reads */ + } + si_pm4_set_reg(pm4, R_02807C_DB_RMI_L2_CACHE_CONTROL, S_02807C_Z_WR_POLICY(V_02807C_CACHE_STREAM_WR) | S_02807C_S_WR_POLICY(V_02807C_CACHE_STREAM_WR) | - S_02807C_HTILE_WR_POLICY(V_02807C_CACHE_STREAM_WR) | + S_02807C_HTILE_WR_POLICY(meta_write_policy) | S_02807C_ZPCPSD_WR_POLICY(V_02807C_CACHE_STREAM_WR) | S_02807C_Z_RD_POLICY(V_02807C_CACHE_NOA_RD) | S_02807C_S_RD_POLICY(V_02807C_CACHE_NOA_RD) | - S_02807C_HTILE_RD_POLICY(V_02807C_CACHE_NOA_RD)); + S_02807C_HTILE_RD_POLICY(meta_read_policy)); si_pm4_set_reg(pm4, R_028410_CB_RMI_GL2_CACHE_CONTROL, - S_028410_CMASK_WR_POLICY(V_028410_CACHE_STREAM_WR) | - S_028410_FMASK_WR_POLICY(V_028410_CACHE_STREAM_WR) | - S_028410_DCC_WR_POLICY(V_028410_CACHE_STREAM_WR) | + S_028410_CMASK_WR_POLICY(meta_write_policy) | + S_028410_FMASK_WR_POLICY(meta_write_policy) | + S_028410_DCC_WR_POLICY(meta_write_policy) | S_028410_COLOR_WR_POLICY(V_028410_CACHE_STREAM_WR) | - S_028410_CMASK_RD_POLICY(V_028410_CACHE_NOA_RD) | - S_028410_FMASK_RD_POLICY(V_028410_CACHE_NOA_RD) | - S_028410_DCC_RD_POLICY(V_028410_CACHE_NOA_RD) | + S_028410_CMASK_RD_POLICY(meta_read_policy) | + S_028410_FMASK_RD_POLICY(meta_read_policy) | + S_028410_DCC_RD_POLICY(meta_read_policy) | S_028410_COLOR_RD_POLICY(V_028410_CACHE_NOA_RD)); si_pm4_set_reg(pm4, R_028428_CB_COVERAGE_OUT_CONTROL, 0); |