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authorKenneth Graunke <[email protected]>2016-03-31 00:53:21 -0700
committerKenneth Graunke <[email protected]>2016-03-31 16:45:07 -0700
commita57320a9ba4f453c567716bf8270c0ac629ad0d2 (patch)
treee24d47651f1c08dcffb344e0aac8efc5fa83a039 /src
parent58d4751fa0c5a38069879e9f72047b75f8351d93 (diff)
i965: Use brw->urb.min_vs_urb_entries instead of 32 for BLORP.
Haswell GT2 and GT3 have a minimum of 64 entries. Hardcoding 32 is not legal. v2: Delete stale comment (caught by Alejandro). Cc: [email protected] Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Topi Pohjolainen <[email protected]>
Diffstat (limited to 'src')
-rw-r--r--src/mesa/drivers/dri/i965/gen7_blorp.cpp5
1 files changed, 1 insertions, 4 deletions
diff --git a/src/mesa/drivers/dri/i965/gen7_blorp.cpp b/src/mesa/drivers/dri/i965/gen7_blorp.cpp
index 89b73ca7519..eae1e30e150 100644
--- a/src/mesa/drivers/dri/i965/gen7_blorp.cpp
+++ b/src/mesa/drivers/dri/i965/gen7_blorp.cpp
@@ -55,11 +55,8 @@ gen7_blorp_emit_urb_config(struct brw_context *brw)
0 /* gs_size */,
urb_size / 2 /* fs_size */);
- /* The minimum valid number of VS entries is 32. See 3DSTATE_URB_VS, Dword
- * 1.15:0 "VS Number of URB Entries".
- */
gen7_emit_urb_state(brw,
- 32 /* num_vs_entries */,
+ brw->urb.min_vs_entries /* num_vs_entries */,
2 /* vs_size */,
2 /* vs_start */,
0 /* num_hs_entries */,