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authorKenneth Graunke <[email protected]>2012-08-07 09:32:46 -0700
committerKenneth Graunke <[email protected]>2012-08-08 09:24:19 -0700
commita2cdd5ada8ae315acbc4225398b7cbf78181f610 (patch)
tree0b48c745bbc31a27e537b8326b92f1721d5876a5 /src
parentc4c78c275abffe8d1014b1355f02239859d6aa2b (diff)
i965: Emit a CS stall before timestamp writes.
This implements one of the Sandybridge PIPE_CONTROL workarounds. It doesn't appear to be required for Ivybridge. Signed-off-by: Kenneth Graunke <[email protected]> Signed-off-by: Daniel Vetter <[email protected]> Reviewed-by: Daniel Vetter <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
Diffstat (limited to 'src')
-rw-r--r--src/mesa/drivers/dri/i965/brw_queryobj.c14
1 files changed, 14 insertions, 0 deletions
diff --git a/src/mesa/drivers/dri/i965/brw_queryobj.c b/src/mesa/drivers/dri/i965/brw_queryobj.c
index afa30914f93..cbe67adf9da 100644
--- a/src/mesa/drivers/dri/i965/brw_queryobj.c
+++ b/src/mesa/drivers/dri/i965/brw_queryobj.c
@@ -49,6 +49,20 @@ static void
write_timestamp(struct intel_context *intel, drm_intel_bo *query_bo, int idx)
{
if (intel->gen >= 6) {
+ /* Emit workaround flushes: */
+ if (intel->gen == 6) {
+ /* The timestamp write below is a non-zero post-sync op, which on
+ * Gen6 necessitates a CS stall. CS stalls need stall at scoreboard
+ * set. See the comments for intel_emit_post_sync_nonzero_flush().
+ */
+ BEGIN_BATCH(4);
+ OUT_BATCH(_3DSTATE_PIPE_CONTROL | (4 - 2));
+ OUT_BATCH(PIPE_CONTROL_CS_STALL | PIPE_CONTROL_STALL_AT_SCOREBOARD);
+ OUT_BATCH(0);
+ OUT_BATCH(0);
+ ADVANCE_BATCH();
+ }
+
BEGIN_BATCH(5);
OUT_BATCH(_3DSTATE_PIPE_CONTROL | (5 - 2));
OUT_BATCH(PIPE_CONTROL_WRITE_TIMESTAMP);