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authorGrigori Goronzy <[email protected]>2016-10-12 00:47:20 +0200
committerDave Airlie <[email protected]>2016-10-12 09:00:22 +1000
commita22b5f28fbcc3cda9c756dec339c7e729d1d10f3 (patch)
tree3fc101487af79016515446cf409b26270c0a7e54 /src
parent0b539abcf4e4aebddddb15862dcadfc727679d5e (diff)
radv: fix strict aliasing violation
Signed-off-by: Dave Airlie <[email protected]>
Diffstat (limited to 'src')
-rw-r--r--src/amd/vulkan/radv_pipeline_cache.c7
1 files changed, 5 insertions, 2 deletions
diff --git a/src/amd/vulkan/radv_pipeline_cache.c b/src/amd/vulkan/radv_pipeline_cache.c
index 032a7e46040..85a2b6dc918 100644
--- a/src/amd/vulkan/radv_pipeline_cache.c
+++ b/src/amd/vulkan/radv_pipeline_cache.c
@@ -28,7 +28,10 @@
#include "ac_nir_to_llvm.h"
struct cache_entry {
- unsigned char sha1[20];
+ union {
+ unsigned char sha1[20];
+ uint32_t sha1_dw[5];
+ };
uint32_t code_size;
struct ac_shader_variant_info variant_info;
struct ac_shader_config config;
@@ -185,7 +188,7 @@ radv_pipeline_cache_set_entry(struct radv_pipeline_cache *cache,
struct cache_entry *entry)
{
const uint32_t mask = cache->table_size - 1;
- const uint32_t start = (*(uint32_t *) entry->sha1);
+ const uint32_t start = entry->sha1_dw[0];
/* We'll always be able to insert when we get here. */
assert(cache->kernel_count < cache->table_size / 2);