i965/fs: Add support for compr4 MRF writes.

These reduce an emitted (not decoded) instruction per shader on
g4x/gen5, but may allow for additional register coalescing as well.

Reviewed-by: Kenneth Graunke <[email protected]>

1 files changed, 18 insertions, 14 deletions

diff --git a/src/mesa/drivers/dri/i965/brw_fs.cpp b/src/mesa/drivers/dri/i965/brw_fs.cpp
index 4e3adbc0a69..2784e0d96bc 100644
--- a/src/mesa/drivers/dri/i965/brw_fs.cpp
+++ b/src/mesa/drivers/dri/i965/brw_fs.cpp
@@ -2073,22 +2073,26 @@ fs_visitor::emit_color_write(int index, int first_color_mrf, fs_reg color)
        * m + 5: g1
        * m + 6: b1
        * m + 7: a1
-       *
-       * By setting the high bit of the MRF register number,
-       * we could indicate that we want COMPR4 mode - instead
-       * of doing the usual destination + 1 for the second
-       * half we would get destination + 4.  We would need to
-       * clue the optimizer into that, though.
        */
-      push_force_uncompressed();
-      emit(BRW_OPCODE_MOV, fs_reg(MRF, first_color_mrf + index), color);
-      pop_force_uncompressed();
+      if (brw->has_compr4) {
+	 /* By setting the high bit of the MRF register number, we
+	  * indicate that we want COMPR4 mode - instead of doing the
+	  * usual destination + 1 for the second half we get
+	  * destination + 4.
+	  */
+	 emit(BRW_OPCODE_MOV,
+	      fs_reg(MRF, BRW_MRF_COMPR4 + first_color_mrf + index), color);
+      } else {
+	 push_force_uncompressed();
+	 emit(BRW_OPCODE_MOV, fs_reg(MRF, first_color_mrf + index), color);
+	 pop_force_uncompressed();
 
-      push_force_sechalf();
-      color.sechalf = true;
-      emit(BRW_OPCODE_MOV, fs_reg(MRF, first_color_mrf + index + 4), color);
-      pop_force_sechalf();
-      color.sechalf = false;
+	 push_force_sechalf();
+	 color.sechalf = true;
+	 emit(BRW_OPCODE_MOV, fs_reg(MRF, first_color_mrf + index + 4), color);
+	 pop_force_sechalf();
+	 color.sechalf = false;
+      }
    }
 }