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authorAnuj Phogat <[email protected]>2015-12-11 19:14:24 -0800
committerAnuj Phogat <[email protected]>2016-05-26 10:57:09 -0700
commit97f0f91cc191d9d024588458f23a229b91acb84d (patch)
tree34fc97ff8a58300b87db59b23ea1721f1dd7665c /src
parentc52e92ec3a37c9ab3fb35132e62e1ddf6a770c27 (diff)
i965/gen9: Remove the halign/valign field setup code in fast copy blit
Experimentation with different values of src/dst horizontal/vertical alignment showed that these fileds are not used on gen9 hardware. A recent update in graphics specs has removed these fields from XY_FAST_COPY_BLT command. Cc: Ben Widawsky <[email protected]> Cc: Chad Versace <[email protected]> Signed-off-by: Anuj Phogat <[email protected]> Reviewed-by: Ben Widawsky <[email protected]>
Diffstat (limited to 'src')
-rw-r--r--src/mesa/drivers/dri/i965/intel_blit.c65
1 files changed, 0 insertions, 65 deletions
diff --git a/src/mesa/drivers/dri/i965/intel_blit.c b/src/mesa/drivers/dri/i965/intel_blit.c
index 72cf9af5b53..4296222878d 100644
--- a/src/mesa/drivers/dri/i965/intel_blit.c
+++ b/src/mesa/drivers/dri/i965/intel_blit.c
@@ -104,64 +104,6 @@ br13_for_cpp(int cpp)
}
}
-static uint32_t
-get_tr_horizontal_align(uint32_t tr_mode, uint32_t cpp, bool is_src) {
- /* Alignment tables for YF/YS tiled surfaces. */
- const uint32_t align_2d_yf[] = {64, 64, 32, 32, 16};
- const uint32_t bpp = cpp * 8;
- const uint32_t shift = is_src ? 17 : 10;
- uint32_t align;
- int i = 0;
-
- if (tr_mode == INTEL_MIPTREE_TRMODE_NONE)
- return 0;
-
- /* Compute array index. */
- assert (bpp >= 8 && bpp <= 128 && _mesa_is_pow_two(bpp));
- i = ffs(bpp / 8) - 1;
-
- align = tr_mode == INTEL_MIPTREE_TRMODE_YF ?
- align_2d_yf[i] :
- 4 * align_2d_yf[i];
-
- assert(_mesa_is_pow_two(align));
-
- /* XY_FAST_COPY_BLT doesn't support horizontal alignment of 16. */
- if (align == 16)
- align = 32;
-
- return (ffs(align) - 6) << shift;
-}
-
-static uint32_t
-get_tr_vertical_align(uint32_t tr_mode, uint32_t cpp, bool is_src) {
- /* Vertical alignment tables for YF/YS tiled surfaces. */
- const unsigned align_2d_yf[] = {64, 32, 32, 16, 16};
- const uint32_t bpp = cpp * 8;
- const uint32_t shift = is_src ? 15 : 8;
- uint32_t align;
- int i = 0;
-
- if (tr_mode == INTEL_MIPTREE_TRMODE_NONE)
- return 0;
-
- /* Compute array index. */
- assert (bpp >= 8 && bpp <= 128 && _mesa_is_pow_two(bpp));
- i = ffs(bpp / 8) - 1;
-
- align = tr_mode == INTEL_MIPTREE_TRMODE_YF ?
- align_2d_yf[i] :
- 4 * align_2d_yf[i];
-
- assert(_mesa_is_pow_two(align));
-
- /* XY_FAST_COPY_BLT doesn't support vertical alignments of 16 and 32. */
- if (align == 16 || align == 32)
- align = 64;
-
- return (ffs(align) - 7) << shift;
-}
-
/**
* Emits the packet for switching the blitter from X to Y tiled or back.
*
@@ -457,13 +399,6 @@ xy_blit_cmd(uint32_t src_tiling, uint32_t src_tr_mode,
if (src_tiling != I915_TILING_NONE)
SET_TILING_XY_FAST_COPY_BLT(src_tiling, src_tr_mode, XY_FAST_SRC);
-
- CMD |= get_tr_horizontal_align(src_tr_mode, cpp, true /* is_src */);
- CMD |= get_tr_vertical_align(src_tr_mode, cpp, true /* is_src */);
-
- CMD |= get_tr_horizontal_align(dst_tr_mode, cpp, false /* is_src */);
- CMD |= get_tr_vertical_align(dst_tr_mode, cpp, false /* is_src */);
-
} else {
assert(cpp <= 4);
switch (cpp) {