diff options
| author | Rafael Antognolli <[email protected]> | 2019-11-05 15:34:53 -0800 |
|---|---|---|
| committer | Jordan Justen <[email protected]> | 2020-06-22 11:42:00 -0700 |
| commit | 793b40924161130bedb1a4ff746a8790004304d8 (patch) | |
| tree | 6cf722467029c35ae5df219075eb192d2ee60f58 /src | |
| parent | 3daa86675124b6b91c108b52e78d032deae1ef15 (diff) | |
intel/isl: Update mocs for DG1
Reviewed-by: Jordan Justen <[email protected]>
Acked-by: Lionel Landwerlin <[email protected]>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4956>
Diffstat (limited to 'src')
| -rw-r--r-- | src/intel/isl/isl.c | 19 |
1 files changed, 14 insertions, 5 deletions
diff --git a/src/intel/isl/isl.c b/src/intel/isl/isl.c index f7689d5b867..e9731616bb1 100644 --- a/src/intel/isl/isl.c +++ b/src/intel/isl/isl.c @@ -99,11 +99,20 @@ static void isl_device_setup_mocs(struct isl_device *dev) { if (dev->info->gen >= 12) { - /* TODO: Set PTE to MOCS 61 when the kernel is ready */ - /* TC=1/LLC Only, LeCC=1/Uncacheable, LRUM=0, L3CC=1/Uncacheable */ - dev->mocs.external = 3 << 1; - /* TC=LLC/eLLC, LeCC=WB, LRUM=3, L3CC=WB */ - dev->mocs.internal = 2 << 1; + if (dev->info->is_dg1) { + /* L3CC=WB */ + dev->mocs.internal = 5 << 1; + /* Displayables on DG1 are free to cache in L3 since L3 is transient + * and flushed at bottom of each submission. + */ + dev->mocs.external = 5 << 1; + } else { + /* TODO: Set PTE to MOCS 61 when the kernel is ready */ + /* TC=1/LLC Only, LeCC=1/Uncacheable, LRUM=0, L3CC=1/Uncacheable */ + dev->mocs.external = 3 << 1; + /* TC=LLC/eLLC, LeCC=WB, LRUM=3, L3CC=WB */ + dev->mocs.internal = 2 << 1; + } } else if (dev->info->gen >= 9) { /* TC=LLC/eLLC, LeCC=PTE, LRUM=3, L3CC=WB */ dev->mocs.external = 1 << 1; |