intel/isl: Add a separate ISL_AUX_USAGE_STC_CCS

Stencil CCS is slightly different from color CCS.  Using a color CCS
resolve with stencil CCS doesn't do the right thing and you can't sample
from a stencil CCS image without the DepthStencilResource bit set or you
will get the wrong data.  Stencil CCS also has it's own rules such as it
doesn't support fast-clear and has no partial resolve.  This seems to
indicate that it should probably be its own isl_aux_usage.  Now that
adding new isl_aux_usage values is pretty cheap, let's split stencil CCS
out on its own.

Reviewed-by: Nanley Chery <[email protected]>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4056>

6 files changed, 31 insertions, 4 deletions

diff --git a/src/intel/blorp/blorp_genX_exec.h b/src/intel/blorp/blorp_genX_exec.h
index a77cff3716c..cc032e6dba8 100644
--- a/src/intel/blorp/blorp_genX_exec.h
+++ b/src/intel/blorp/blorp_genX_exec.h
@@ -1805,7 +1805,8 @@ blorp_emit_gen8_hiz_op(struct blorp_batch *batch,
          hzp.DepthBufferResolveEnable = params->depth.enabled;
 #if GEN_GEN >= 12
          if (params->stencil.enabled) {
-            assert(params->stencil.aux_usage == ISL_AUX_USAGE_CCS_E);
+            assert(params->stencil.aux_usage == ISL_AUX_USAGE_CCS_E ||
+                   params->stencil.aux_usage == ISL_AUX_USAGE_STC_CCS);
             hzp.StencilBufferResolveEnable = true;
          }
 #endif
diff --git a/src/intel/isl/isl.h b/src/intel/isl/isl.h
index 596ec75c4af..aabf980b86a 100644
--- a/src/intel/isl/isl.h
+++ b/src/intel/isl/isl.h
@@ -648,6 +648,12 @@ enum isl_aux_usage {
     * @invariant isl_surf::samples > 1
     */
    ISL_AUX_USAGE_MCS_CCS,
+
+   /** CCS auxiliary data is used to compress a stencil buffer
+    *
+    * @invariant isl_surf::samples == 1
+    */
+   ISL_AUX_USAGE_STC_CCS,
 };
 
 /**
@@ -1779,7 +1785,8 @@ isl_aux_usage_has_ccs(enum isl_aux_usage usage)
           usage == ISL_AUX_USAGE_MC ||
           usage == ISL_AUX_USAGE_HIZ_CCS_WT ||
           usage == ISL_AUX_USAGE_HIZ_CCS ||
-          usage == ISL_AUX_USAGE_MCS_CCS;
+          usage == ISL_AUX_USAGE_MCS_CCS ||
+          usage == ISL_AUX_USAGE_STC_CCS;
 }
 
 static inline bool
diff --git a/src/intel/isl/isl_aux_info.c b/src/intel/isl/isl_aux_info.c
index 556827b97bf..1155fee0325 100644
--- a/src/intel/isl/isl_aux_info.c
+++ b/src/intel/isl/isl_aux_info.c
@@ -71,6 +71,7 @@ static const struct aux_usage_info info[] = {
    AUX(         COMPRESS, Y, Y, Y, Y, CCS_E)
    AUX(RESOLVE_AMBIGUATE, x, Y, x, Y, CCS_D)
    AUX(RESOLVE_AMBIGUATE, Y, x, x, Y, MC)
+   AUX(         COMPRESS, Y, x, x, Y, STC_CCS)
 };
 #undef x
 #undef Y
diff --git a/src/intel/isl/isl_emit_depth_stencil.c b/src/intel/isl/isl_emit_depth_stencil.c
index 9615a34f718..3921543e1ad 100644
--- a/src/intel/isl/isl_emit_depth_stencil.c
+++ b/src/intel/isl/isl_emit_depth_stencil.c
@@ -165,7 +165,8 @@ isl_genX(emit_depth_stencil_hiz_s)(const struct isl_device *dev, void *batch,
       sb.SurfLOD = info->view->base_level;
       sb.MinimumArrayElement = info->view->base_array_layer;
       sb.StencilCompressionEnable =
-         info->stencil_aux_usage == ISL_AUX_USAGE_CCS_E;
+         info->stencil_aux_usage == ISL_AUX_USAGE_CCS_E ||
+         info->stencil_aux_usage == ISL_AUX_USAGE_STC_CCS;
       sb.ControlSurfaceEnable = sb.StencilCompressionEnable;
 #elif GEN_GEN >= 8 || GEN_IS_HASWELL
       sb.StencilBufferEnable = true;
diff --git a/src/intel/isl/isl_surface_state.c b/src/intel/isl/isl_surface_state.c
index 63ee7b10d2f..0145be160c7 100644
--- a/src/intel/isl/isl_surface_state.c
+++ b/src/intel/isl/isl_surface_state.c
@@ -93,6 +93,7 @@ static const uint32_t isl_to_gen_aux_mode[] = {
    [ISL_AUX_USAGE_CCS_E] = AUX_CCS_E,
    [ISL_AUX_USAGE_HIZ_CCS_WT] = AUX_CCS_E,
    [ISL_AUX_USAGE_MCS_CCS] = AUX_MCS_LCE,
+   [ISL_AUX_USAGE_STC_CCS] = AUX_CCS_E,
 };
 #elif GEN_GEN >= 9
 static const uint32_t isl_to_gen_aux_mode[] = {
@@ -561,7 +562,8 @@ isl_genX(surf_fill_state_s)(const struct isl_device *dev, void *state,
          assert(info->aux_usage == ISL_AUX_USAGE_MCS ||
                 info->aux_usage == ISL_AUX_USAGE_CCS_E ||
                 info->aux_usage == ISL_AUX_USAGE_HIZ_CCS_WT ||
-                info->aux_usage == ISL_AUX_USAGE_MCS_CCS);
+                info->aux_usage == ISL_AUX_USAGE_MCS_CCS ||
+                info->aux_usage == ISL_AUX_USAGE_STC_CCS);
       } else if (GEN_GEN >= 9) {
          assert(info->aux_usage == ISL_AUX_USAGE_HIZ ||
                 info->aux_usage == ISL_AUX_USAGE_MCS ||
diff --git a/src/intel/isl/tests/isl_aux_info_test.cpp b/src/intel/isl/tests/isl_aux_info_test.cpp
index c1c4e203e70..47e41d8b8c6 100644
--- a/src/intel/isl/tests/isl_aux_info_test.cpp
+++ b/src/intel/isl/tests/isl_aux_info_test.cpp
@@ -389,6 +389,21 @@ TEST(StateTransitionWrite, WritesCompress) {
    E(PASS_THROUGH, MCS, true, COMPRESSED_NO_CLEAR);
    E(AUX_INVALID, MCS, false, ASSERT);
    E(AUX_INVALID, MCS, true, ASSERT);
+
+   E(CLEAR, STC_CCS, false, ASSERT);
+   E(CLEAR, STC_CCS, true, ASSERT);
+   E(PARTIAL_CLEAR, STC_CCS, false, ASSERT);
+   E(PARTIAL_CLEAR, STC_CCS, true, ASSERT);
+   E(COMPRESSED_CLEAR, STC_CCS, false, ASSERT);
+   E(COMPRESSED_CLEAR, STC_CCS, true, ASSERT);
+   E(COMPRESSED_NO_CLEAR, STC_CCS, false, COMPRESSED_NO_CLEAR);
+   E(COMPRESSED_NO_CLEAR, STC_CCS, true, COMPRESSED_NO_CLEAR);
+   E(RESOLVED, STC_CCS, false, COMPRESSED_NO_CLEAR);
+   E(RESOLVED, STC_CCS, true, COMPRESSED_NO_CLEAR);
+   E(PASS_THROUGH, STC_CCS, false, COMPRESSED_NO_CLEAR);
+   E(PASS_THROUGH, STC_CCS, true, COMPRESSED_NO_CLEAR);
+   E(AUX_INVALID, STC_CCS, false, ASSERT);
+   E(AUX_INVALID, STC_CCS, true, ASSERT);
 }
 
 TEST(StateTransitionWrite, WritesResolveAmbiguate) {