diff options
| author | Alyssa Rosenzweig <[email protected]> | 2020-05-21 15:48:03 -0400 |
|---|---|---|
| committer | Alyssa Rosenzweig <[email protected]> | 2020-05-21 15:48:03 -0400 |
| commit | 6dd11a6dc34c624a90de3e064ad3552830a8d0d9 (patch) | |
| tree | 93886aaa4b71c15e770058da70217dd985e9ee73 /src | |
| parent | b8bd356dff032ea3a67158f133fc24da39c9e0b7 (diff) | |
panfrost: Limit blend shader work count
To 8, but later we should go much lower.
Signed-off-by: Alyssa Rosenzweig <[email protected]>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5124>
Diffstat (limited to 'src')
| -rw-r--r-- | src/gallium/drivers/panfrost/pan_cmdstream.c | 9 | ||||
| -rw-r--r-- | src/panfrost/midgard/midgard_ra.c | 9 |
2 files changed, 13 insertions, 5 deletions
diff --git a/src/gallium/drivers/panfrost/pan_cmdstream.c b/src/gallium/drivers/panfrost/pan_cmdstream.c index 50eaa195a69..21ab118085d 100644 --- a/src/gallium/drivers/panfrost/pan_cmdstream.c +++ b/src/gallium/drivers/panfrost/pan_cmdstream.c @@ -642,12 +642,15 @@ panfrost_frag_meta_blend_update(struct panfrost_context *ctx, blend[c] = panfrost_get_blend_for_context(ctx, c, &shader_bo, &shader_offset); - /* If there is a blend shader, work registers are shared. XXX: opt */ + /* If there is a blend shader, work registers are shared. We impose 8 + * work registers as a limit for blend shaders. Should be lower XXX */ if (!(dev->quirks & IS_BIFROST)) { for (unsigned c = 0; c < rt_count; ++c) { - if (blend[c].is_shader) - fragmeta->midgard1.work_count = 16; + if (blend[c].is_shader) { + fragmeta->midgard1.work_count = + MAX2(fragmeta->midgard1.work_count, 8); + } } } diff --git a/src/panfrost/midgard/midgard_ra.c b/src/panfrost/midgard/midgard_ra.c index baeec45f042..8c6210e0634 100644 --- a/src/panfrost/midgard/midgard_ra.c +++ b/src/panfrost/midgard/midgard_ra.c @@ -442,8 +442,10 @@ static struct lcra_state * allocate_registers(compiler_context *ctx, bool *spilled) { /* The number of vec4 work registers available depends on when the - * uniforms start, so compute that first */ - int work_count = 16 - MAX2((ctx->uniform_cutoff - 8), 0); + * uniforms start and the shader stage. By ABI we limit blend shaders + * to 8 registers, should be lower XXX */ + int work_count = ctx->is_blend ? 8 : + 16 - MAX2((ctx->uniform_cutoff - 8), 0); /* No register allocation to do with no SSA */ @@ -831,6 +833,9 @@ mir_spill_register( unsigned spill_class, unsigned *spill_count) { + if (spill_class == REG_CLASS_WORK && ctx->is_blend) + unreachable("Blend shader spilling is currently unimplemented"); + unsigned spill_index = ctx->temp_count; /* We have a spill node, so check the class. Work registers |