diff options
| author | Kenneth Graunke <[email protected]> | 2011-06-08 16:05:34 -0700 |
|---|---|---|
| committer | Kenneth Graunke <[email protected]> | 2011-06-18 17:53:52 -0700 |
| commit | 6c947cfd1973c3791d54f1406c973357b4a9621a (patch) | |
| tree | b52faddf1b501f7505a99413600dc0966aa6dc3c /src | |
| parent | 2f4a4b943f1cad9bbbb8f66c34dca506503ba5bb (diff) | |
i965/fs: Add support for non-shadow textureGrad (TXD) on gen4.
Signed-off-by: Kenneth Graunke <[email protected]>
Reviewed-by: Eric Anholt <[email protected]>
Diffstat (limited to 'src')
| -rw-r--r-- | src/mesa/drivers/dri/i965/brw_fs_emit.cpp | 4 | ||||
| -rw-r--r-- | src/mesa/drivers/dri/i965/brw_fs_visitor.cpp | 37 |
2 files changed, 39 insertions, 2 deletions
diff --git a/src/mesa/drivers/dri/i965/brw_fs_emit.cpp b/src/mesa/drivers/dri/i965/brw_fs_emit.cpp index 844b89b7dc3..1c522cbad02 100644 --- a/src/mesa/drivers/dri/i965/brw_fs_emit.cpp +++ b/src/mesa/drivers/dri/i965/brw_fs_emit.cpp @@ -312,7 +312,9 @@ fs_visitor::generate_tex(fs_inst *inst, struct brw_reg dst, struct brw_reg src) } break; case FS_OPCODE_TXD: - assert(!"TXD isn't supported on gen4 yet."); + assert(!inst->shadow_compare); // not supported yet + assert(inst->mlen == 7 || inst->mlen == 10); + msg_type = BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE_GRADIENTS; break; } } diff --git a/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp b/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp index 638eaa416c8..a5479e1178b 100644 --- a/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp +++ b/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp @@ -595,7 +595,42 @@ fs_visitor::emit_texture_gen4(ir_texture *ir, fs_reg dst, fs_reg coordinate, /* gen4's SIMD8 sampler always has the slots for u,v,r present. */ mlen += 3; } else if (ir->op == ir_txd) { - assert(!"TXD isn't supported on gen4 yet."); + ir->lod_info.grad.dPdx->accept(this); + fs_reg dPdx = this->result; + + ir->lod_info.grad.dPdy->accept(this); + fs_reg dPdy = this->result; + + for (int i = 0; i < ir->coordinate->type->vector_elements; i++) { + emit(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen + i), coordinate); + coordinate.reg_offset++; + } + /* the slots for u and v are always present, but r is optional */ + mlen += MAX2(ir->coordinate->type->vector_elements, 2); + + /* P = u, v, r + * dPdx = dudx, dvdx, drdx + * dPdy = dudy, dvdy, drdy + * + * 2-arg: dudx dvdx dudy dvdy + * dPdx.x dPdx.y dPdy.x dPdy.y + * m4 m5 m6 m7 + * + * 3-arg: dudx dvdx drdx dudy dvdy drdy + * dPdx.x dPdx.y dPdx.z dPdy.x dPdy.y dPdy.z + * m5 m6 m7 m8 m9 m10 + */ + for (int i = 0; i < ir->lod_info.grad.dPdx->type->vector_elements; i++) { + emit(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen), dPdx); + dPdx.reg_offset++; + mlen++; + } + + for (int i = 0; i < ir->lod_info.grad.dPdy->type->vector_elements; i++) { + emit(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen), dPdy); + dPdy.reg_offset++; + mlen++; + } } else { /* Oh joy. gen4 doesn't have SIMD8 non-shadow-compare bias/lod * instructions. We'll need to do SIMD16 here. |