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authorJason Ekstrand <[email protected]>2016-03-03 16:15:54 -0800
committerJason Ekstrand <[email protected]>2016-03-03 16:16:57 -0800
commit56ba13c994fc3b1c4058bb99656dad6fa2aa819d (patch)
tree5d6fb396b54c7c568baa14ae87a85a386a2a3720 /src
parent623ce595a97cc3ec47be042867e24047162cd371 (diff)
isl/surface_state: Set L2 bypass disable for certain BC* formats
Diffstat (limited to 'src')
-rw-r--r--src/intel/isl/isl_surface_state.c22
1 files changed, 22 insertions, 0 deletions
diff --git a/src/intel/isl/isl_surface_state.c b/src/intel/isl/isl_surface_state.c
index 0f45100fba3..1607aa6233d 100644
--- a/src/intel/isl/isl_surface_state.c
+++ b/src/intel/isl/isl_surface_state.c
@@ -370,6 +370,28 @@ isl_genX(surf_fill_state_s)(const struct isl_device *dev, void *state,
s.MIPCountLOD = MAX(info->view->levels, 1) - 1;
}
+#if GEN_GEN >= 8
+ /* From the CHV PRM, Volume 2d, page 321 (RENDER_SURFACE_STATE dword 0
+ * bit 9 "Sampler L2 Bypass Mode Disable" Programming Notes):
+ *
+ * This bit must be set for the following surface types: BC2_UNORM
+ * BC3_UNORM BC5_UNORM BC5_SNORM BC7_UNORM
+ */
+ if (GEN_GEN >= 9 || dev->info->is_cherryview) {
+ switch (info->view->format) {
+ case ISL_FORMAT_BC2_UNORM:
+ case ISL_FORMAT_BC3_UNORM:
+ case ISL_FORMAT_BC5_UNORM:
+ case ISL_FORMAT_BC5_SNORM:
+ case ISL_FORMAT_BC7_UNORM:
+ s.SamplerL2BypassModeDisable = true;
+ break;
+ default:
+ break;
+ }
+ }
+#endif
+
#if 0
if (GEN_GEN == 8) {
if (isl_format_is_integer(info->view->format)) {