i965g: fixes to build after merge of master

18 files changed, 112 insertions, 101 deletions

diff --git a/src/gallium/auxiliary/util/u_upload_mgr.h b/src/gallium/auxiliary/util/u_upload_mgr.h
index d414a1f2f62..e158bed9d04 100644
--- a/src/gallium/auxiliary/util/u_upload_mgr.h
+++ b/src/gallium/auxiliary/util/u_upload_mgr.h
@@ -32,7 +32,7 @@
 #ifndef U_UPLOAD_MGR_H
 #define U_UPLOAD_MGR_H
 
-#include "pipe/p_error.h"
+#include "pipe/p_defines.h"
 
 struct pipe_screen;
 struct pipe_buffer;
diff --git a/src/gallium/drivers/i965/brw_clip_state.c b/src/gallium/drivers/i965/brw_clip_state.c
index 467364e8849..5c3ccfd8d0d 100644
--- a/src/gallium/drivers/i965/brw_clip_state.c
+++ b/src/gallium/drivers/i965/brw_clip_state.c
@@ -69,7 +69,7 @@ clip_unit_populate_key(struct brw_context *brw, struct brw_clip_unit_key *key)
    key->urb_size = brw->urb.vsize;
 
    /*  */
-   key->depth_clamp = 0; // XXX: add this to gallium: ctx->Transform.DepthClamp;
+   key->depth_clamp = 0; /* XXX: add this to gallium: ctx->Transform.DepthClamp; */
 }
 
 static enum pipe_error
diff --git a/src/gallium/drivers/i965/brw_context.h b/src/gallium/drivers/i965/brw_context.h
index 143e068987c..56e78074000 100644
--- a/src/gallium/drivers/i965/brw_context.h
+++ b/src/gallium/drivers/i965/brw_context.h
@@ -197,7 +197,7 @@ struct brw_fragment_shader {
    struct brw_immediate_data immediates;
 
    unsigned iz_lookup;
-   //unsigned wm_lookup;
+   /*unsigned wm_lookup;*/
    
    unsigned  uses_depth:1;
    unsigned  has_flow_control:1;
@@ -722,7 +722,7 @@ struct brw_context
       /** Input sizes, calculated from active vertex program.
        * One bit per fragment program input attribute.
        */
-      //GLbitfield input_size_masks[4];
+      /*GLbitfield input_size_masks[4];*/
 
       /** Array of surface default colors (texture border color) */
       struct brw_winsys_buffer *sdc_bo[BRW_MAX_TEX_UNIT];
diff --git a/src/gallium/drivers/i965/brw_draw.c b/src/gallium/drivers/i965/brw_draw.c
index 4498773dd86..852fd229828 100644
--- a/src/gallium/drivers/i965/brw_draw.c
+++ b/src/gallium/drivers/i965/brw_draw.c
@@ -108,7 +108,7 @@ static int brw_emit_prim(struct brw_context *brw,
       prim_packet.start_vert_location += brw->ib.start_vertex_offset;
    prim_packet.instance_count = 1;
    prim_packet.start_instance_location = 0;
-   prim_packet.base_vert_location = 0; // prim->basevertex; XXX: add this to gallium
+   prim_packet.base_vert_location = 0; /* prim->basevertex; XXX: add this to gallium */
 
 
    /* If we're set to always flush, do it before and after the primitive emit.
diff --git a/src/gallium/drivers/i965/brw_eu.h b/src/gallium/drivers/i965/brw_eu.h
index 565f4ef1c59..af509b2e5f4 100644
--- a/src/gallium/drivers/i965/brw_eu.h
+++ b/src/gallium/drivers/i965/brw_eu.h
@@ -34,7 +34,7 @@
 #define BRW_EU_H
 
 #include "util/u_debug.h"
-#include "pipe/p_error.h"
+#include "pipe/p_defines.h"
 
 #include "brw_structs.h"
 #include "brw_defines.h"
diff --git a/src/gallium/drivers/i965/brw_eu_emit.c b/src/gallium/drivers/i965/brw_eu_emit.c
index 3ee50899fba..4fe7b6acc16 100644
--- a/src/gallium/drivers/i965/brw_eu_emit.c
+++ b/src/gallium/drivers/i965/brw_eu_emit.c
@@ -200,7 +200,7 @@ void brw_set_src1( struct brw_instruction *insn,
        * in the future:
        */
       assert (reg.address_mode == BRW_ADDRESS_DIRECT);
-      //assert (reg.file == BRW_GENERAL_REGISTER_FILE);
+      /*assert (reg.file == BRW_GENERAL_REGISTER_FILE); */
 
       if (insn->header.access_mode == BRW_ALIGN_1) {
 	 insn->bits3.da1.src1_subreg_nr = reg.subnr;
diff --git a/src/gallium/drivers/i965/brw_pipe_sampler.c b/src/gallium/drivers/i965/brw_pipe_sampler.c
index 5cd38a43a68..5ddc63f57ec 100644
--- a/src/gallium/drivers/i965/brw_pipe_sampler.c
+++ b/src/gallium/drivers/i965/brw_pipe_sampler.c
@@ -204,15 +204,29 @@ static void brw_set_sampler_textures(struct pipe_context *pipe,
    brw->state.dirty.mesa |= PIPE_NEW_BOUND_TEXTURES;
 }
 
+static void brw_set_vertex_sampler_textures(struct pipe_context *pipe,
+                                            unsigned num,
+                                            struct pipe_texture **texture)
+{
+}
+
+static void brw_bind_vertex_sampler_state(struct pipe_context *pipe,
+                                          unsigned num, void **sampler)
+{
+}
+
 
 void brw_pipe_sampler_init( struct brw_context *brw )
 {
-   brw->base.set_sampler_textures = brw_set_sampler_textures;
    brw->base.create_sampler_state = brw_create_sampler_state;
-   brw->base.bind_sampler_states = brw_bind_sampler_state;
    brw->base.delete_sampler_state = brw_delete_sampler_state;
 
-   brw->base.set_sampler_textures = brw_set_sampler_textures;
+   brw->base.set_fragment_sampler_textures = brw_set_sampler_textures;
+   brw->base.bind_fragment_sampler_states = brw_bind_sampler_state;
+
+   brw->base.set_vertex_sampler_textures = brw_set_vertex_sampler_textures;
+   brw->base.bind_vertex_sampler_states = brw_bind_vertex_sampler_state;
+
 }
 void brw_pipe_sampler_cleanup( struct brw_context *brw )
 {
diff --git a/src/gallium/drivers/i965/brw_screen.c b/src/gallium/drivers/i965/brw_screen.c
index 3d96a77d656..0ecacac9a3a 100644
--- a/src/gallium/drivers/i965/brw_screen.c
+++ b/src/gallium/drivers/i965/brw_screen.c
@@ -396,7 +396,7 @@ brw_create_screen(struct brw_winsys_screen *sws, uint pci_id)
    brw_screen_tex_surface_init(bscreen);
    brw_screen_buffer_init(bscreen);
 
-   bscreen->no_tiling = debug_get_option("BRW_NO_TILING", FALSE);
+   bscreen->no_tiling = debug_get_option("BRW_NO_TILING", FALSE) != NULL;
    
    
    return &bscreen->base;
diff --git a/src/gallium/drivers/i965/brw_screen_surface.c b/src/gallium/drivers/i965/brw_screen_surface.c
index 1e37c63d6c9..e2b9954e596 100644
--- a/src/gallium/drivers/i965/brw_screen_surface.c
+++ b/src/gallium/drivers/i965/brw_screen_surface.c
@@ -31,6 +31,7 @@
 
 #include "util/u_memory.h"
 #include "util/u_simple_list.h"
+#include "util/u_math.h"
 
 #include "pipe/p_screen.h"
 #include "brw_screen.h"
@@ -138,8 +139,8 @@ static struct brw_surface *create_in_place_view( struct brw_screen *brw_screen,
    assert(id.bits.zslice == 0);
 
    surface->base.format = tex->base.format;
-   surface->base.width = tex->base.width[id.bits.level];
-   surface->base.height = tex->base.height[id.bits.level];
+   surface->base.width = u_minify(tex->base.width0, id.bits.level);
+   surface->base.height = u_minify(tex->base.height0, id.bits.level);
    surface->base.offset = tex->image_offset[id.bits.level][id.bits.face];
    surface->base.usage = usage;
    surface->base.zslice = id.bits.zslice;
diff --git a/src/gallium/drivers/i965/brw_screen_tex_layout.c b/src/gallium/drivers/i965/brw_screen_tex_layout.c
index 71a8890f833..894f4bea401 100644
--- a/src/gallium/drivers/i965/brw_screen_tex_layout.c
+++ b/src/gallium/drivers/i965/brw_screen_tex_layout.c
@@ -110,10 +110,6 @@ brw_tex_set_level_info(struct brw_texture *tex,
    assert(tex->image_offset[level] == NULL);
    assert(nr_images >= 1);
 
-   tex->base.width[level] = w;
-   tex->base.height[level] = h;
-   tex->base.depth[level] = d;
-
    tex->level_offset[level] = (x + y * tex->pitch) * tex->cpp;
    tex->nr_images[level] = nr_images;
 
@@ -147,14 +143,14 @@ static void brw_layout_2d( struct brw_texture *tex )
    GLuint level;
    GLuint x = 0;
    GLuint y = 0;
-   GLuint width = tex->base.width[0];
-   GLuint height = tex->base.height[0];
+   GLuint width = tex->base.width0;
+   GLuint height = tex->base.height0;
 
-   tex->pitch = tex->base.width[0];
+   tex->pitch = tex->base.width0;
    brw_tex_alignment_unit(tex->base.format, &align_w, &align_h);
 
    if (tex->compressed) {
-       tex->pitch = align(tex->base.width[0], align_w);
+       tex->pitch = align(tex->base.width0, align_w);
    }
 
    /* May need to adjust pitch to accomodate the placement of
@@ -166,11 +162,11 @@ static void brw_layout_2d( struct brw_texture *tex )
        GLuint mip1_width;
 
        if (tex->compressed) {
-           mip1_width = align(minify(tex->base.width[0]), align_w)
-               + align(minify(minify(tex->base.width[0])), align_w);
+          mip1_width = (align(u_minify(tex->base.width0, 1), align_w) + 
+                        align(u_minify(tex->base.width0, 2), align_w));
        } else {
-           mip1_width = align(minify(tex->base.width[0]), align_w)
-               + minify(minify(tex->base.width[0]));
+          mip1_width = (align(u_minify(tex->base.width0, 1), align_w) + 
+                        u_minify(tex->base.width0, 2));
        }
 
        if (mip1_width > tex->pitch) {
@@ -209,8 +205,8 @@ static void brw_layout_2d( struct brw_texture *tex )
 	 y += img_height;
       }
 
-      width  = minify(width);
-      height = minify(height);
+      width  = u_minify(width, 1);
+      height = u_minify(height, 1);
    }
 }
 
@@ -222,28 +218,28 @@ brw_layout_cubemap_idgng( struct brw_texture *tex )
    GLuint level;
    GLuint x = 0;
    GLuint y = 0;
-   GLuint width = tex->base.width[0];
-   GLuint height = tex->base.height[0];
+   GLuint width = tex->base.width0;
+   GLuint height = tex->base.height0;
    GLuint qpitch = 0;
    GLuint y_pitch = 0;
 
-   tex->pitch = tex->base.width[0];
+   tex->pitch = tex->base.width0;
    brw_tex_alignment_unit(tex->base.format, &align_w, &align_h);
    y_pitch = align(height, align_h);
 
    if (tex->compressed) {
-      tex->pitch = align(tex->base.width[0], align_w);
+      tex->pitch = align(tex->base.width0, align_w);
    }
 
    if (tex->base.last_level != 0) {
       GLuint mip1_width;
 
       if (tex->compressed) {
-	 mip1_width = (align(minify(tex->base.width[0]), align_w) +
-		       align(minify(minify(tex->base.width[0])), align_w));
+	 mip1_width = (align(u_minify(tex->base.width0, 1), align_w) +
+		       align(u_minify(tex->base.width0, 2), align_w));
       } else {
-	 mip1_width = (align(minify(tex->base.width[0]), align_w) +
-		       minify(minify(tex->base.width[0])));
+	 mip1_width = (align(u_minify(tex->base.width0, 1), align_w) +
+		       u_minify(tex->base.width0, 2));
       }
 
       if (mip1_width > tex->pitch) {
@@ -255,19 +251,19 @@ brw_layout_cubemap_idgng( struct brw_texture *tex )
 
    if (tex->compressed) {
       qpitch = ((y_pitch + 
-		 align(minify(y_pitch), align_h) +
+		 align(u_minify(y_pitch, 1), align_h) +
 		 11 * align_h) / 4) * tex->pitch * tex->cpp;
 
       tex->total_height = ((y_pitch + 
-			    align(minify(y_pitch), align_h) + 
+			    align(u_minify(y_pitch, 1), align_h) + 
 			    11 * align_h) / 4) * 6;
    } else {
       qpitch = (y_pitch + 
-		align(minify(y_pitch), align_h) + 
+		align(u_minify(y_pitch, 1), align_h) + 
 		11 * align_h) * tex->pitch * tex->cpp;
 
       tex->total_height = (y_pitch +
-			   align(minify(y_pitch), align_h) +
+			   align(u_minify(y_pitch, 1), align_h) +
 			   11 * align_h) * 6;
    }
 
@@ -293,8 +289,8 @@ brw_layout_cubemap_idgng( struct brw_texture *tex )
 	 y += img_height;
       }
 
-      width  = minify(width);
-      height = minify(height);
+      width  = u_minify(width, 1);
+      height = u_minify(height, 1);
    }
 
    return TRUE;
@@ -304,9 +300,9 @@ brw_layout_cubemap_idgng( struct brw_texture *tex )
 static boolean
 brw_layout_3d_cube( struct brw_texture *tex )
 {
-   GLuint width  = tex->base.width[0];
-   GLuint height = tex->base.height[0];
-   GLuint depth = tex->base.depth[0];
+   GLuint width  = tex->base.width0;
+   GLuint height = tex->base.height0;
+   GLuint depth = tex->base.depth0;
    GLuint pack_x_pitch, pack_x_nr;
    GLuint pack_y_pitch;
    GLuint level;
@@ -320,8 +316,8 @@ brw_layout_3d_cube( struct brw_texture *tex )
       tex->pitch = align(width, align_w);
       pack_y_pitch = (height + 3) / 4;
    } else {
-      tex->pitch = brw_tex_pitch_align(tex, tex->base.width[0]);
-      pack_y_pitch = align(tex->base.height[0], align_h);
+      tex->pitch = brw_tex_pitch_align(tex, tex->base.width0);
+      pack_y_pitch = align(tex->base.height0, align_h);
    }
 
    pack_x_pitch = width;
@@ -349,9 +345,9 @@ brw_layout_3d_cube( struct brw_texture *tex )
 
 
       tex->total_height += y;
-      width  = minify(width);
-      height = minify(height);
-      depth  = minify(depth);
+      width  = u_minify(width, 1);
+      height = u_minify(height, 1);
+      depth  = u_minify(depth, 1);
 
       if (tex->compressed) {
 	 pack_y_pitch = (height + 3) / 4;
diff --git a/src/gallium/drivers/i965/brw_screen_texture.c b/src/gallium/drivers/i965/brw_screen_texture.c
index f4c20f31a53..ff999086c02 100644
--- a/src/gallium/drivers/i965/brw_screen_texture.c
+++ b/src/gallium/drivers/i965/brw_screen_texture.c
@@ -259,8 +259,8 @@ static struct pipe_texture *brw_texture_create( struct pipe_screen *screen,
     */
    tex->ss.ss1.base_addr = 0; /* reloc */
    tex->ss.ss2.mip_count = tex->base.last_level;
-   tex->ss.ss2.width = tex->base.width[0] - 1;
-   tex->ss.ss2.height = tex->base.height[0] - 1;
+   tex->ss.ss2.width = tex->base.width0 - 1;
+   tex->ss.ss2.height = tex->base.height0 - 1;
 
    switch (tex->tiling) {
    case BRW_TILING_NONE:
@@ -278,7 +278,7 @@ static struct pipe_texture *brw_texture_create( struct pipe_screen *screen,
    }
 
    tex->ss.ss3.pitch = (tex->pitch * tex->cpp) - 1;
-   tex->ss.ss3.depth = tex->base.depth[0] - 1;
+   tex->ss.ss3.depth = tex->base.depth0 - 1;
 
    tex->ss.ss4.min_lod = 0;
  
@@ -478,7 +478,7 @@ brw_texture_blanket_winsys_buffer(struct pipe_screen *screen,
 
    if (templ->target != PIPE_TEXTURE_2D ||
        templ->last_level != 0 ||
-       templ->depth[0] != 1)
+       templ->depth0 != 1)
       return NULL;
 
    if (pf_is_compressed(templ->format))
@@ -529,8 +529,8 @@ brw_texture_blanket_winsys_buffer(struct pipe_screen *screen,
     */
    tex->ss.ss1.base_addr = 0; /* reloc */
    tex->ss.ss2.mip_count = tex->base.last_level;
-   tex->ss.ss2.width = tex->base.width[0] - 1;
-   tex->ss.ss2.height = tex->base.height[0] - 1;
+   tex->ss.ss2.width = tex->base.width0 - 1;
+   tex->ss.ss2.height = tex->base.height0 - 1;
 
    switch (tex->tiling) {
    case BRW_TILING_NONE:
@@ -548,7 +548,7 @@ brw_texture_blanket_winsys_buffer(struct pipe_screen *screen,
    }
 
    tex->ss.ss3.pitch = (tex->pitch * tex->cpp) - 1;
-   tex->ss.ss3.depth = tex->base.depth[0] - 1;
+   tex->ss.ss3.depth = tex->base.depth0 - 1;
 
    tex->ss.ss4.min_lod = 0;
 
diff --git a/src/gallium/drivers/i965/brw_state.h b/src/gallium/drivers/i965/brw_state.h
index a9b8165495e..d2bbd0123d1 100644
--- a/src/gallium/drivers/i965/brw_state.h
+++ b/src/gallium/drivers/i965/brw_state.h
@@ -33,12 +33,12 @@
 #ifndef BRW_STATE_H
 #define BRW_STATE_H
 
-#include "pipe/p_error.h"
+#include "pipe/p_defines.h"
 #include "util/u_memory.h"
 
 #include "brw_context.h"
 
-static inline void
+static INLINE void
 brw_add_validated_bo(struct brw_context *brw, struct brw_winsys_buffer *bo)
 {
    assert(brw->state.validated_bo_count < Elements(brw->state.validated_bos));
diff --git a/src/gallium/drivers/i965/brw_state_upload.c b/src/gallium/drivers/i965/brw_state_upload.c
index bf65ca1cf2a..f8b91eff816 100644
--- a/src/gallium/drivers/i965/brw_state_upload.c
+++ b/src/gallium/drivers/i965/brw_state_upload.c
@@ -38,7 +38,7 @@
 
 const struct brw_tracked_state *atoms[] =
 {
-//   &brw_wm_input_sizes,
+/*   &brw_wm_input_sizes, */
    &brw_vs_prog,
    &brw_gs_prog, 
    &brw_clip_prog, 
@@ -56,7 +56,7 @@ const struct brw_tracked_state *atoms[] =
    &brw_cc_unit,
 
    &brw_vs_surfaces,		/* must do before unit */
-   //&brw_wm_constant_surface,	/* must do before wm surfaces/bind bo */
+   /*&brw_wm_constant_surface,*/	/* must do before wm surfaces/bind bo */
    &brw_wm_surfaces,		/* must do before samplers and unit */
    &brw_wm_samplers,
 
diff --git a/src/gallium/drivers/i965/brw_vs_emit.c b/src/gallium/drivers/i965/brw_vs_emit.c
index 6d8366f8624..1d0fff0d9ea 100644
--- a/src/gallium/drivers/i965/brw_vs_emit.c
+++ b/src/gallium/drivers/i965/brw_vs_emit.c
@@ -1067,22 +1067,22 @@ static struct brw_reg get_arg( struct brw_vs_compile *c,
 {
    struct brw_reg reg;
 
-   if (src->SrcRegister.File == TGSI_FILE_NULL)
+   if (src->Register.File == TGSI_FILE_NULL)
       return brw_null_reg();
 
    reg = get_src_reg(c, argIndex,
-		     src->SrcRegister.File,
-		     src->SrcRegister.Index,
-		     src->SrcRegister.Indirect);
+		     src->Register.File,
+		     src->Register.Index,
+		     src->Register.Indirect);
 
    /* Convert 3-bit swizzle to 2-bit.  
     */
-   reg.dw1.bits.swizzle = BRW_SWIZZLE4(src->SrcRegister.SwizzleX,
-				       src->SrcRegister.SwizzleY,
-				       src->SrcRegister.SwizzleZ,
-				       src->SrcRegister.SwizzleW);
+   reg.dw1.bits.swizzle = BRW_SWIZZLE4(src->Register.SwizzleX,
+				       src->Register.SwizzleY,
+				       src->Register.SwizzleZ,
+				       src->Register.SwizzleW);
 
-   reg.negate = src->SrcRegister.Negate ? 1 : 0;   
+   reg.negate = src->Register.Negate ? 1 : 0;   
 
    /* XXX: abs, absneg
     */
@@ -1353,7 +1353,7 @@ static void emit_insn(struct brw_vs_compile *c,
 		      const struct tgsi_full_instruction *inst)
 {
    unsigned opcode = inst->Instruction.Opcode;
-   unsigned label = inst->InstructionExtLabel.Label;
+   unsigned label = inst->Label.Label;
    struct brw_compile *p = &c->func;
    struct brw_reg args[3], dst;
    GLuint i;
@@ -1366,7 +1366,7 @@ static void emit_insn(struct brw_vs_compile *c,
    /* Get argument regs.
     */
    for (i = 0; i < 3; i++) {
-      args[i] = get_arg(c, &inst->FullSrcRegisters[i], i);
+      args[i] = get_arg(c, &inst->Src[i], i);
    }
 
    /* Get dest regs.  Note that it is possible for a reg to be both
@@ -1374,9 +1374,9 @@ static void emit_insn(struct brw_vs_compile *c,
     * care needs to be taken emitting multi-operation instructions.
     */ 
    dst = get_dst(c, 
-		 inst->FullDstRegisters[0].DstRegister.File,
-		 inst->FullDstRegisters[0].DstRegister.Index,
-		 inst->FullDstRegisters[0].DstRegister.WriteMask);
+		 inst->Dst[0].Register.File,
+		 inst->Dst[0].Register.Index,
+		 inst->Dst[0].Register.WriteMask);
 
    /* XXX: saturate
     */
@@ -1619,7 +1619,7 @@ void brw_vs_emit(struct brw_vs_compile *c)
    struct tgsi_parse_context parse;
    struct tgsi_full_instruction *inst;
 
-//   if (BRW_DEBUG & DEBUG_VS)
+   if (BRW_DEBUG & DEBUG_VS)
       tgsi_dump(c->vp->tokens, 0); 
 
    c->stack_index = brw_indirect(0, 0);
diff --git a/src/gallium/drivers/i965/brw_winsys.h b/src/gallium/drivers/i965/brw_winsys.h
index af506a283dc..2f470677163 100644
--- a/src/gallium/drivers/i965/brw_winsys.h
+++ b/src/gallium/drivers/i965/brw_winsys.h
@@ -27,7 +27,7 @@
 #define BRW_WINSYS_H
 
 #include "pipe/p_compiler.h"
-#include "pipe/p_error.h"
+#include "pipe/p_defines.h"
 #include "pipe/p_refcnt.h"
 
 struct brw_winsys;
diff --git a/src/gallium/drivers/i965/brw_wm.c b/src/gallium/drivers/i965/brw_wm.c
index 2c9d3e5e87e..fdf820a9aae 100644
--- a/src/gallium/drivers/i965/brw_wm.c
+++ b/src/gallium/drivers/i965/brw_wm.c
@@ -180,7 +180,7 @@ static enum pipe_error do_wm_prog( struct brw_context *brw,
       /* XXX: GLSL support
        */
       exit(1);
-      //brw_wm_branching_shader_emit(brw, c);
+      /* brw_wm_branching_shader_emit(brw, c); */
    }
    else {
       c->dispatch_width = 16;
diff --git a/src/gallium/drivers/i965/brw_wm_emit.c b/src/gallium/drivers/i965/brw_wm_emit.c
index 0b82f4e1562..7e57d0306bc 100644
--- a/src/gallium/drivers/i965/brw_wm_emit.c
+++ b/src/gallium/drivers/i965/brw_wm_emit.c
@@ -1007,7 +1007,7 @@ static void emit_killp( struct brw_wm_compile *c )
 
    brw_push_insn_state(p);
    brw_set_mask_control(p, BRW_MASK_DISABLE);
-   brw_NOT(p, c->emit_mask_reg, brw_mask_reg(1)); //IMASK
+   brw_NOT(p, c->emit_mask_reg, brw_mask_reg(1)); /* IMASK */
    brw_AND(p, r0uw, c->emit_mask_reg, r0uw);
    brw_pop_insn_state(p);
 }
diff --git a/src/gallium/drivers/i965/brw_wm_fp.c b/src/gallium/drivers/i965/brw_wm_fp.c
index a8b5e15f366..9c5b527f897 100644
--- a/src/gallium/drivers/i965/brw_wm_fp.c
+++ b/src/gallium/drivers/i965/brw_wm_fp.c
@@ -957,15 +957,15 @@ static struct brw_fp_dst translate_dst( struct brw_wm_compile *c,
 {
    struct brw_fp_dst out;
 
-   out.file = dst->DstRegister.File;
-   out.index = dst->DstRegister.Index;
-   out.writemask = dst->DstRegister.WriteMask;
-   out.indirect = dst->DstRegister.Indirect;
+   out.file = dst->Register.File;
+   out.index = dst->Register.Index;
+   out.writemask = dst->Register.WriteMask;
+   out.indirect = dst->Register.Indirect;
    out.saturate = (saturate == TGSI_SAT_ZERO_ONE);
    
    if (out.indirect) {
-      assert(dst->DstRegisterInd.File == TGSI_FILE_ADDRESS);
-      assert(dst->DstRegisterInd.Index == 0);
+      assert(dst->Indirect.File == TGSI_FILE_ADDRESS);
+      assert(dst->Indirect.Index == 0);
    }
    
    return out;
@@ -977,14 +977,14 @@ static struct brw_fp_src translate_src( struct brw_wm_compile *c,
 {
    struct brw_fp_src out;
 
-   out.file = src->SrcRegister.File;
-   out.index = src->SrcRegister.Index;
-   out.indirect = src->SrcRegister.Indirect;
+   out.file = src->Register.File;
+   out.index = src->Register.Index;
+   out.indirect = src->Register.Indirect;
 
-   out.swizzle = ((src->SrcRegister.SwizzleX << 0) |
-		  (src->SrcRegister.SwizzleY << 2) |
-		  (src->SrcRegister.SwizzleZ << 4) |
-		  (src->SrcRegister.SwizzleW << 6));
+   out.swizzle = ((src->Register.SwizzleX << 0) |
+		  (src->Register.SwizzleY << 2) |
+		  (src->Register.SwizzleZ << 4) |
+		  (src->Register.SwizzleW << 6));
    
    switch (tgsi_util_get_full_src_register_sign_mode( src, 0 )) {
    case TGSI_UTIL_SIGN_CLEAR:
@@ -1010,8 +1010,8 @@ static struct brw_fp_src translate_src( struct brw_wm_compile *c,
    }
 
    if (out.indirect) {
-      assert(src->SrcRegisterInd.File == TGSI_FILE_ADDRESS);
-      assert(src->SrcRegisterInd.Index == 0);
+      assert(src->Indirect.File == TGSI_FILE_ADDRESS);
+      assert(src->Indirect.Index == 0);
    }
    
    return out;
@@ -1027,11 +1027,11 @@ static void emit_insn( struct brw_wm_compile *c,
    struct brw_fp_src src[3];
    int i;
 
-   dst = translate_dst( c, &inst->FullDstRegisters[0],
+   dst = translate_dst( c, &inst->Dst[0],
 			inst->Instruction.Saturate );
 
    for (i = 0; i < inst->Instruction.NumSrcRegs; i++)
-      src[i] = translate_src( c, &inst->FullSrcRegisters[i] );
+      src[i] = translate_src( c, &inst->Src[i] );
    
    switch (opcode) {
    case TGSI_OPCODE_ABS:
@@ -1063,7 +1063,7 @@ static void emit_insn( struct brw_wm_compile *c,
 
    case TGSI_OPCODE_TEX:
       precalc_tex(c, dst,
-		  inst->InstructionExtTexture.Texture,
+		  inst->Texture.Texture,
 		  src[1].index,	/* use sampler unit for tex idx */
 		  src[0],       /* coord */
                   src[1]);      /* sampler */
@@ -1071,7 +1071,7 @@ static void emit_insn( struct brw_wm_compile *c,
 
    case TGSI_OPCODE_TXP:
       precalc_txp(c, dst,
-		  inst->InstructionExtTexture.Texture,
+		  inst->Texture.Texture,
 		  src[1].index,	/* use sampler unit for tex idx */
 		  src[0],       /* coord */
                   src[1]);      /* sampler */
@@ -1081,7 +1081,7 @@ static void emit_insn( struct brw_wm_compile *c,
       /* XXX: TXB not done
        */
       precalc_tex(c, dst,
-		  inst->InstructionExtTexture.Texture,
+		  inst->Texture.Texture,
 		  src[1].index,	/* use sampler unit for tex idx*/
 		  src[0],
                   src[1]);
@@ -1169,14 +1169,14 @@ int brw_wm_pass_fp( struct brw_wm_compile *c )
             unsigned first, last, mask;
             unsigned attrib;
 
-            first = decl->DeclarationRange.First;
-            last = decl->DeclarationRange.Last;
+            first = decl->Range.First;
+            last = decl->Range.Last;
             mask = decl->Declaration.UsageMask;
 
             for (attrib = first; attrib <= last; attrib++) {
 	       emit_interp(c, 
 			   attrib, 
-			   decl->Semantic.SemanticName,
+			   decl->Semantic.Name,
 			   decl->Declaration.Interpolate );
             }
          }