aboutsummaryrefslogtreecommitdiffstats
path: root/src
diff options
context:
space:
mode:
authorEric Anholt <[email protected]>2012-12-18 13:45:14 -0800
committerEric Anholt <[email protected]>2012-12-22 13:46:04 -0800
commit0d6a722ec4df73595d4159e5b35c6fd61f847a6c (patch)
treeaeec2254b4555cd05317beb2bf9f6f5ee10622c1 /src
parente454b2d480c4ef875cd0800b12a0b4cd37821cb5 (diff)
i965: Add perf debug for depth/stencil alignment workaround.
Fixing these rendering bugs has been implicated in performance regressions (which may be unfixable), but at least knowing that it's happening should help diagnose those regressions. Reviewed-by: Jordan Justen <[email protected]>
Diffstat (limited to 'src')
-rw-r--r--src/mesa/drivers/dri/i965/brw_misc_state.c16
1 files changed, 16 insertions, 0 deletions
diff --git a/src/mesa/drivers/dri/i965/brw_misc_state.c b/src/mesa/drivers/dri/i965/brw_misc_state.c
index b0a19181fc3..d7724e3e07b 100644
--- a/src/mesa/drivers/dri/i965/brw_misc_state.c
+++ b/src/mesa/drivers/dri/i965/brw_misc_state.c
@@ -370,6 +370,10 @@ brw_workaround_depthstencil_alignment(struct brw_context *brw)
}
if (rebase_depth) {
+ perf_debug("HW workaround: blitting depth level %d to a temporary "
+ "to fix alignment (depth tile offset %d,%d)\n",
+ depth_irb->mt_level, tile_x, tile_y);
+
intel_renderbuffer_move_to_temp(intel, depth_irb);
/* In the case of stencil_irb being the same packed depth/stencil
* texture but not the same rb, make it point at our rebased mt, too.
@@ -427,6 +431,10 @@ brw_workaround_depthstencil_alignment(struct brw_context *brw)
}
if (rebase_stencil) {
+ perf_debug("HW workaround: blitting stencil level %d to a temporary "
+ "to fix alignment (stencil tile offset %d,%d)\n",
+ stencil_irb->mt_level, stencil_tile_x, stencil_tile_y);
+
intel_renderbuffer_move_to_temp(intel, stencil_irb);
stencil_mt = get_stencil_miptree(stencil_irb);
@@ -443,6 +451,14 @@ brw_workaround_depthstencil_alignment(struct brw_context *brw)
} else if (depth_irb && !rebase_depth) {
if (tile_x != stencil_tile_x ||
tile_y != stencil_tile_y) {
+ perf_debug("HW workaround: blitting depth level %d to a temporary "
+ "to match stencil level %d alignment (depth tile offset "
+ "%d,%d, stencil offset %d,%d)\n",
+ depth_irb->mt_level,
+ stencil_irb->mt_level,
+ tile_x, tile_y,
+ stencil_tile_x, stencil_tile_y);
+
intel_renderbuffer_move_to_temp(intel, depth_irb);
tile_x = depth_irb->draw_x & tile_mask_x;