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authorNanley Chery <[email protected]>2016-07-06 11:13:15 -0700
committerNanley Chery <[email protected]>2016-07-15 10:35:40 -0700
commit028f6d8317f00a94b09df81e8f2cb944077e64a7 (patch)
treeaebcd1e3957c0d0969c34634095dd1652066cec3 /src
parent96c664cd03aa59adfecb0478c192097ab07c42d6 (diff)
isl: Fix assert on raw buffer surface state size
See inline PRM reference. Cc: 12.0 <[email protected]> Signed-off-by: Nanley Chery <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
Diffstat (limited to 'src')
-rw-r--r--src/intel/isl/isl_surface_state.c9
1 files changed, 8 insertions, 1 deletions
diff --git a/src/intel/isl/isl_surface_state.c b/src/intel/isl/isl_surface_state.c
index fc7e1bae026..58e9af5f8ee 100644
--- a/src/intel/isl/isl_surface_state.c
+++ b/src/intel/isl/isl_surface_state.c
@@ -460,8 +460,15 @@ isl_genX(buffer_fill_state_s)(void *state,
uint32_t num_elements = info->size / info->stride;
if (GEN_GEN >= 7) {
+ /* From the IVB PRM, SURFACE_STATE::Height,
+ *
+ * For typed buffer and structured buffer surfaces, the number
+ * of entries in the buffer ranges from 1 to 2^27. For raw buffer
+ * surfaces, the number of entries in the buffer is the number of bytes
+ * which can range from 1 to 2^30.
+ */
if (info->format == ISL_FORMAT_RAW) {
- assert(num_elements <= (1ull << 31));
+ assert(num_elements <= (1ull << 30));
assert((num_elements & 3) == 0);
} else {
assert(num_elements <= (1ull << 27));