diff options
| author | Jason Ekstrand <[email protected]> | 2018-03-23 09:27:55 -0700 |
|---|---|---|
| committer | Jason Ekstrand <[email protected]> | 2018-03-30 17:20:27 -0700 |
| commit | 2b977989f3f01c186677988494bbf9b7342b31f2 (patch) | |
| tree | a0626511f7b87c956ec7e9cee15a83ebca320413 /src | |
| parent | 6018f5b07966a0f85dea1ee6775d50a8c85fdee1 (diff) | |
intel/vec4: Set channel_sizes for MOV_INDIRECT sources
Otherwise, any indirect push constant access results in an assertion
failure when we start digging through the channel_sizes array. This
fixes dEQP-VK.pipeline.push_constant.graphics_pipeline.dynamic_index_vert
on Haswell. It should be a harmless no-op for GL since indirect push
constants aren't used there.
Reviewed-by: Kenneth Graunke <[email protected]>
Fixes: e69e5c7006d "i965/vec4: load dvec3/4 uniforms first in the..."
Diffstat (limited to 'src')
| -rw-r--r-- | src/intel/compiler/brw_vec4.cpp | 5 |
1 files changed, 4 insertions, 1 deletions
diff --git a/src/intel/compiler/brw_vec4.cpp b/src/intel/compiler/brw_vec4.cpp index 2f352a1118f..218925ccb12 100644 --- a/src/intel/compiler/brw_vec4.cpp +++ b/src/intel/compiler/brw_vec4.cpp @@ -695,8 +695,11 @@ vec4_visitor::pack_uniform_registers() * the next part of our packing algorithm. */ int reg = inst->src[0].nr; - for (unsigned i = 0; i < vec4s_read; i++) + int channel_size = type_sz(inst->src[0].type) / 4; + for (unsigned i = 0; i < vec4s_read; i++) { chans_used[reg + i] = 4; + channel_sizes[reg + i] = MAX2(channel_sizes[reg + i], channel_size); + } } } |